 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ddr2 sdram mt47h128m4 C 32 meg x 4 x 4 banks mt47h64m8 C 16 meg x 8 x 4 banks mt47h32m16 C 8 meg x 16 x 4 banks features ? v dd = +1.8v 0.1v, v ddq = +1.8v 0.1v ? jedec-standard 1.8v i/o (sstl_18-compatible) ? differential data strobe (dqs, dqs#) option ? 4 n -bit prefetch architecture ? duplicate output strobe (rdqs) option for x8 ? dll to align dq and dqs transitions with ck ? 4 internal banks for concurrent operation ? programmable cas latency (cl) ? posted cas additive latency (al) ? write latency = read latency - 1 t ck ? selectable burst lengths: 4 or 8 ? adjustable data-output drive strength ? 64ms, 8192-cycle refresh ? on-die termination (odt) ? industrial temperature (it) option ? automotive temperature (at) option ? rohs-compliant ? supports jedec clock jitter specification options 1 marking ? configuration C 128 meg x 4 (32 meg x 4 x 4 banks) 128m4 C 64 meg x 8 (16 meg x 8 x 4 banks) 64m8 C 32 meg x 16 (8 meg x 16 x 4 banks) 32m16 ? fbga package (pb-free) C x16 C 84-ball fbga (8mm x 12.5mm) rev. f, g hr ? fbga package (pb-free) C x4, x8 C 60-ball fbga (8mm x 10mm) rev. f, g cf ? fbga package (lead solder) C x16 C 84-ball fbga (8mm x 12.5mm) rev. f, g hw ? fbga package (lead solder) C x4, x8 C 60-ball fbga (8mm x 10mm) rev. f, g jn ? timing C cycle time C 1.875ns @ cl = 7 (ddr2-1066) -187e C 2.5ns @ cl = 5 (ddr2-800) -25e C 2.5ns @ cl = 6 (ddr2-800) -25 C 3.0ns @ cl = 4 (ddr2-667) -3e C 3.0ns @ cl = 5 (ddr2-667) -3 C 3.75ns @ cl = 4 (ddr2-533) -37e ? self refresh C standard none C low-power l ? operating temperature C commercial (0c t c 85c) none C industrial (C40c t c 95c; C40c t a 85c) it C automotive (C40c t c , t a 105c) at ? revision :f/:g note: 1. not all options listed can be combined to define an offered product. use the part catalog search on www.micron.com for product offerings and availability. 512mb: x4, x8, x16 ddr2 sdram features pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
table 1: key timing parameters speed grade data rate (mt/s) t rc (ns) cl = 3 cl = 4 cl = 5 cl = 6 -187e 400 533 800 1066 54 -25e 400 533 800 800 55 -25 400 533 667 800 55 -3e 400 667 667 n/a 54 -3 400 533 667 n/a 55 -37e 400 533 n/a n/a 55 table 2: addressing parameter 128 meg x 4 64 meg x 8 32 meg x 16 configuration 32 meg x 4 x 4 banks 16 meg x 8 x 4 banks 8 meg x 16 x 4 banks refresh count 8k 8k 8k row address a[13:0] (16k) a[13:0] (16k) a[12:0] (8k) bank address ba[1:0] (4) ba[1:0] (4) ba[1:0] (4) column address a[11, 9:0] (2k) a[9:0] (1k) a[9:0] (1k) figure 1: 512mb ddr2 part numbers example part number: mt47h128m4hr-25e :g configuration 128 meg x 4 64 meg x 8 32 meg x 16 128m4 64m8 32m16 speed grade t ck = 3.75ns, cl = 4 t ck = 3ns, cl = 5 t ck = 3ns, cl = 4 t ck = 2.5ns, cl = 6 t ck = 2.5ns, cl = 5 -37e -3 -3e -25 -25e - configuration mt47h package speed revision : { package pb-free 84-ball 8mm x 12.5mm fbga 60-ball 8mm x 10mm fbga lead solder 84-ball 8mm x 12.5mm fbga 60-ball 8mm x 10mm fbga hr cf hw jn low power industrial temperature automotive temperature l it at revision :f/:g t ck = 1.875ns, cl = 7 -187e note: 1. not all speeds and configurations are available in all packages. 512mb: x4, x8, x16 ddr2 sdram features pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. fbga part number system due to space limitations, fbga-packaged components have an abbreviated part marking that is different from the part number. for a quick conversion of an fbga code, see the fbga part marking decoder on microns web site: http://www.micron.com . 512mb: x4, x8, x16 ddr2 sdram features pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. contents state diagram .................................................................................................................................................. 9 functional description ................................................................................................................................... 10 industrial temperature .............................................................................................................................. 10 automotive temperature ........................................................................................................................... 11 general notes ............................................................................................................................................ 11 functional block diagrams ............................................................................................................................. 12 ball assignments and descriptions ................................................................................................................. 14 packaging ...................................................................................................................................................... 18 package dimensions .................................................................................................................................. 18 fbga package capacitance ......................................................................................................................... 20 electrical specifications C absolute ratings ..................................................................................................... 21 temperature and thermal impedance ........................................................................................................ 21 electrical specifications C i dd parameters ........................................................................................................ 24 i dd specifications and conditions ............................................................................................................... 24 i dd7 conditions .......................................................................................................................................... 24 ac timing operating specifications ................................................................................................................ 31 ac and dc operating conditions .................................................................................................................... 42 odt dc electrical characteristics ................................................................................................................... 43 input electrical characteristics and operating conditions ............................................................................... 44 output electrical characteristics and operating conditions ............................................................................. 47 output driver characteristics ......................................................................................................................... 49 power and ground clamp characteristics ....................................................................................................... 53 ac overshoot/undershoot specification ......................................................................................................... 54 input slew rate derating ................................................................................................................................ 56 commands .................................................................................................................................................... 69 truth tables ............................................................................................................................................... 69 deselect ................................................................................................................................................. 73 no operation (nop) .............................................................................................................................. 74 load mode (lm) ..................................................................................................................................... 74 activate .................................................................................................................................................. 74 read ......................................................................................................................................................... 74 write ....................................................................................................................................................... 74 precharge .............................................................................................................................................. 75 refresh ................................................................................................................................................... 75 self refresh ........................................................................................................................................... 75 mode register (mr) ........................................................................................................................................ 75 burst length .............................................................................................................................................. 76 burst type ................................................................................................................................................. 77 operating mode ......................................................................................................................................... 77 dll reset ................................................................................................................................................. 77 write recovery ........................................................................................................................................... 78 power-down mode .................................................................................................................................... 78 cas latency (cl) ........................................................................................................................................ 79 extended mode register (emr) ....................................................................................................................... 80 dll enable/disable ................................................................................................................................... 81 output drive strength ................................................................................................................................ 81 dqs# enable/disable ................................................................................................................................. 81 rdqs enable/disable ................................................................................................................................. 81 output enable/disable ............................................................................................................................... 81 on-die termination (odt) ........................................................................................................................ 82 512mb: x4, x8, x16 ddr2 sdram features pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. off-chip driver (ocd) impedance calibration ............................................................................................ 82 posted cas additive latency (al) ............................................................................................................... 82 extended mode register 2 (emr2) .................................................................................................................. 84 extended mode register 3 (emr3) .................................................................................................................. 85 initialization .................................................................................................................................................. 86 activate ...................................................................................................................................................... 89 read ............................................................................................................................................................. 91 read with precharge ................................................................................................................................. 95 read with auto precharge .......................................................................................................................... 97 write .......................................................................................................................................................... 102 precharge ................................................................................................................................................. 112 refresh ...................................................................................................................................................... 113 self refresh .............................................................................................................................................. 114 power-down mode ....................................................................................................................................... 116 precharge power-down clock frequency change .......................................................................................... 123 reset ............................................................................................................................................................. 124 cke low anytime ...................................................................................................................................... 124 odt timing .................................................................................................................................................. 126 mrs command to odt update delay ........................................................................................................ 128 512mb: x4, x8, x16 ddr2 sdram features pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. list of figures figure 1: 512mb ddr2 part numbers .............................................................................................................. 2 figure 2: simplified state diagram ................................................................................................................... 9 figure 3: 128 meg x 4 functional block diagram ............................................................................................. 12 figure 4: 64 meg x 8 functional block diagram .............................................................................................. 13 figure 5: 32 meg x 16 functional block diagram ............................................................................................. 13 figure 6: 60-ball fbga C x4, x8 ball assignments (top view) ........................................................................... 14 figure 7: 84-ball fbga C x16 ball assignments (top view) .............................................................................. 15 figure 8: 84-ball fbga (8mm x 12.5mm) C x16 ................................................................................................ 18 figure 9: 60-ball fbga (8mm x 10mm) C x4, x8 ............................................................................................... 19 figure 10: example temperature test point location ..................................................................................... 22 figure 11: single-ended input signal levels ................................................................................................... 44 figure 12: differential input signal levels ...................................................................................................... 45 figure 13: differential output signal levels .................................................................................................... 47 figure 14: output slew rate load .................................................................................................................. 48 figure 15: full strength pull-down characteristics ......................................................................................... 49 figure 16: full strength pull-up characteristics ............................................................................................. 50 figure 17: reduced strength pull-down characteristics ................................................................................. 51 figure 18: reduced strength pull-up characteristics ...................................................................................... 52 figure 19: input clamp characteristics .......................................................................................................... 53 figure 20: overshoot ..................................................................................................................................... 54 figure 21: undershoot .................................................................................................................................. 54 figure 22: nominal slew rate for t is .............................................................................................................. 59 figure 23: tangent line for t is ....................................................................................................................... 59 figure 24: nominal slew rate for t ih .............................................................................................................. 60 figure 25: tangent line for t ih ...................................................................................................................... 60 figure 26: nominal slew rate for t ds ............................................................................................................. 65 figure 27: tangent line for t ds ...................................................................................................................... 65 figure 28: nominal slew rate for t dh ............................................................................................................ 66 figure 29: tangent line for t dh ..................................................................................................................... 66 figure 30: ac input test signal waveform command/address balls ............................................................... 67 figure 31: ac input test signal waveform for data with dqs, dqs# (differential) ........................................... 67 figure 32: ac input test signal waveform for data with dqs (single-ended) .................................................. 68 figure 33: ac input test signal waveform (differential) ................................................................................. 68 figure 34: mr definition ............................................................................................................................... 76 figure 35: cl ................................................................................................................................................ 79 figure 36: emr definition ............................................................................................................................. 80 figure 37: read latency ............................................................................................................................... 83 figure 38: write latency ............................................................................................................................. 83 figure 39: emr2 definition ........................................................................................................................... 84 figure 40: emr3 definition ........................................................................................................................... 85 figure 41: ddr2 power-up and initialization ................................................................................................. 86 figure 42: example: meeting t rrd (min) and t rcd (min) .............................................................................. 89 figure 43: multibank activate restriction ....................................................................................................... 90 figure 44: read latency ............................................................................................................................... 92 figure 45: consecutive read bursts .............................................................................................................. 93 figure 46: nonconsecutive read bursts ........................................................................................................ 94 figure 47: read interrupted by read ........................................................................................................... 95 figure 48: read-to-write ............................................................................................................................ 95 figure 49: read-to-precharge C bl = 4 ...................................................................................................... 96 figure 50: read-to-precharge C bl = 8 ...................................................................................................... 96 512mb: x4, x8, x16 ddr2 sdram features pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 51: bank read C without auto precharge ............................................................................................. 98 figure 52: bank read C with auto precharge ................................................................................................... 99 figure 53: x4, x8 data output timing C t dqsq, t qh, and data valid window ................................................. 100 figure 54: x16 data output timing C t dqsq, t qh, and data valid window ..................................................... 101 figure 55: data output timing C t ac and t dqsck ......................................................................................... 102 figure 56: write burst ................................................................................................................................... 104 figure 57: consecutive write-to-write ...................................................................................................... 105 figure 58: nonconsecutive write-to-write ................................................................................................ 105 figure 59: write interrupted by write ....................................................................................................... 106 figure 60: write-to-read ........................................................................................................................... 107 figure 61: write-to-precharge ................................................................................................................ 108 figure 62: bank write C without auto precharge ............................................................................................ 109 figure 63: bank write C with auto precharge ................................................................................................. 110 figure 64: write C dm operation ................................................................................................................ 111 figure 65: data input timing ........................................................................................................................ 112 figure 66: refresh mode ............................................................................................................................... 113 figure 67: self refresh .................................................................................................................................. 115 figure 68: power-down ................................................................................................................................ 117 figure 69: read-to-power-down or self refresh entry .................................................................................. 119 figure 70: read with auto precharge-to-power-down or self refresh entry .................................................. 119 figure 71: write-to-power-down or self refresh entry ................................................................................ 120 figure 72: write with auto precharge-to-power-down or self refresh entry ................................................. 120 figure 73: refresh command-to-power-down entry ................................................................................. 121 figure 74: activate command-to-power-down entry ................................................................................ 121 figure 75: precharge command-to-power-down entry ............................................................................ 122 figure 76: load mode command-to-power-down entry ............................................................................ 122 figure 77: input clock frequency change during precharge power-down mode ........................................... 123 figure 78: reset function ........................................................................................................................... 125 figure 79: odt timing for entering and exiting power-down mode .............................................................. 127 figure 80: timing for mrs command to odt update delay .......................................................................... 128 figure 81: odt timing for active or fast-exit power-down mode ................................................................. 128 figure 82: odt timing for slow-exit or precharge power-down modes ......................................................... 129 figure 83: odt turn-off timings when entering power-down mode ............................................................ 129 figure 84: odt turn-on timing when entering power-down mode ............................................................. 130 figure 85: odt turn-off timing when exiting power-down mode ............................................................... 131 figure 86: odt turn-on timing when exiting power-down mode ................................................................ 132 512mb: x4, x8, x16 ddr2 sdram features pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. list of tables table 1: key timing parameters ...................................................................................................................... 2 table 2: addressing ......................................................................................................................................... 2 table 3: fbga 84-ball C x16 and 60-ball C x4, x8 descriptions .......................................................................... 16 table 4: input capacitance ............................................................................................................................ 20 table 5: absolute maximum dc ratings ........................................................................................................ 21 table 6: temperature limits .......................................................................................................................... 22 table 7: thermal impedance ......................................................................................................................... 22 table 8: general i dd parameters .................................................................................................................... 24 table 9: i dd7 timing patterns (4-bank interleave read operation) ................................................................. 24 table 10: ddr2 i dd specifications and conditions (die revision f) ................................................................ 25 table 11: ddr2 i dd specifications and conditions (die revision g) ................................................................ 28 table 12: ac operating specifications and conditions .................................................................................... 31 table 13: recommended dc operating conditions (sstl_18) ........................................................................ 42 table 14: odt dc electrical characteristics ................................................................................................... 43 table 15: input dc logic levels ..................................................................................................................... 44 table 16: input ac logic levels ..................................................................................................................... 44 table 17: differential input logic levels ........................................................................................................ 45 table 18: differential ac output parameters .................................................................................................. 47 table 19: output dc current drive ................................................................................................................ 47 table 20: output characteristics .................................................................................................................... 48 table 21: full strength pull-down current (ma) ............................................................................................ 49 table 22: full strength pull-up current (ma) ................................................................................................. 50 table 23: reduced strength pull-down current (ma) ..................................................................................... 51 table 24: reduced strength pull-up current (ma) .......................................................................................... 52 table 25: input clamp characteristics ........................................................................................................... 53 table 26: address and control balls ............................................................................................................... 54 table 27: clock, data, strobe, and mask balls ................................................................................................. 54 table 28: ac input test conditions ................................................................................................................ 55 table 29: ddr2-400/533 setup and hold time derating values ( t is and t ih) ................................................... 57 table 30: ddr2-667/800/1066 setup and hold time derating values ( t is and t ih) .......................................... 58 table 31: ddr2-400/533 t ds, t dh derating values with differential strobe ..................................................... 61 table 32: ddr2-667/800/1066 t ds, t dh derating values with differential strobe ............................................ 62 table 33: single-ended dqs slew rate derating values using t ds b and t dh b .................................................. 63 table 34: single-ended dqs slew rate fully derated (dqs, dq at v ref ) at ddr2-667 ..................................... 63 table 35: single-ended dqs slew rate fully derated (dqs, dq at v ref ) at ddr2-533 ..................................... 64 table 36: single-ended dqs slew rate fully derated (dqs, dq at v ref ) at ddr2-400 ..................................... 64 table 37: truth table C ddr2 commands ..................................................................................................... 69 table 38: truth table C current state bank n C command to bank n ............................................................... 70 table 39: truth table C current state bank n C command to bank m .............................................................. 72 table 40: minimum delay with auto precharge enabled ................................................................................. 73 table 41: burst definition .............................................................................................................................. 77 table 42: read using concurrent auto precharge ......................................................................................... 97 table 43: write using concurrent auto precharge ....................................................................................... 103 table 44: truth table C cke ......................................................................................................................... 118 512mb: x4, x8, x16 ddr2 sdram features pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. state diagram figure 2: simplified state diagram automatic sequence command sequence pre initialization sequence self refreshing cke_l refreshing precharge power- down setting mrs emrs sr cke_h refresh idle all banks precharged cke_l cke_l cke_l (e)mrs ocd default activating act bank active reading read writing write active power- down cke_l cke_l cke_h cke_l writing with auto precharge reading with auto precharge read a write a pre, pre_a write a write a read a pre , pre_a read a read write precharging cke_h write read pre, pre_a act = activate cke_h = cke high, exit power-down or self refresh cke_l = cke low, enter power-down (e)mrs = (extended) mode register set pre = precharge pre_a = precharge all read = read read a = read with auto precharge refresh = refresh sr = self refresh write = write write a = write with auto precharge note: 1. this diagram provides the basic command flow. it is not comprehensive and does not identify all timing requirements or possible command restrictions such as multibank in- teraction, power down, entry/exit, etc. 512mb: x4, x8, x16 ddr2 sdram state diagram pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. functional description the ddr2 sdram uses a double data rate architecture to achieve high-speed opera- tion. the double data rate architecture is essentially a 4 n -prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o balls. a single read or write access for the ddr2 sdram effectively consists of a single 4 n -bit-wide, one- clock-cycle data transfer at the internal dram core and four corresponding n -bit-wide, one-half-clock-cycle data transfers at the i/o balls. a bidirectional data strobe (dqs, dqs#) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr2 sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the x16 offering has two data strobes, one for the lower byte (ldqs, ldqs#) and one for the upper byte (udqs, udqs#). the ddr2 sdram operates from a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. com- mands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs as well as to both edges of ck. read and write accesses to the ddr2 sdram are burst-oriented; accesses start at a se- lected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an activate command, which is then followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr2 sdram provides for programmable read or write burst lengths of four or eight locations. ddr2 sdram supports interrupting a burst read of eight with another read or a burst write of eight with another write. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard ddr sdram, the pipelined, multibank architecture of ddr2 sdram enables concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. a self refresh mode is provided, along with a power-saving, power-down mode. all inputs are compatible with the jedec standard for sstl_18. all full drive-strength outputs are sstl_18-compatible. industrial temperature the industrial temperature (it) option, if offered, has two simultaneous requirements: ambient temperature surrounding the device cannot be less than C40c or greater than +85c, and the case temperature cannot be less than C40c or greater than +95c. je- dec specifications require the refresh rate to double when t c exceeds +85c; this also requires use of the high-temperature self refresh option. additionally, odt resistance, input/output impedance and idd values must be derated when t c is < 0c or > +85c. 512mb: x4, x8, x16 ddr2 sdram functional description pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. automotive temperature the automotive temperature (at) option, if offered, has two simultaneous require- ments: ambient temperature surrounding the device cannot be less than C40c or greater than +105c, and the case temperature cannot be less than C40c or greater than +105c. jedec specifications require the refresh rate to double when t c exceeds +85c; this also requires use of the high-temperature self refresh option. additionally, odt resistance the input/output impedance and idd values must be derated when t c is < 0c or > +85c. general notes ? the functionality and the timing specifications discussed in this data sheet are for the dll-enabled mode of operation. ? throughout the data sheet, the various figures and text refer to dqs as dq. the dq term is to be interpreted as any and all dq collectively, unless specifically stated oth- erwise. additionally, the x16 is divided into 2 bytes: the lower byte and the upper byte. for the lower byte (dq0Cdq7), dm refers to ldm and dqs refers to ldqs. for the upper byte (dq8Cdq15), dm refers to udm and dqs refers to udqs. ? complete functionality is described throughout the document, and any page or dia- gram may have been simplified to convey a topic and may not be inclusive of all requirements. ? any specific requirement takes precedence over a general statement. 512mb: x4, x8, x16 ddr2 sdram functional description pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. functional block diagrams the ddr2 sdram is a high-speed cmos, dynamic random access memory. it is inter- nally configured as a multibank dram. figure 3: 128 meg x 4 functional block diagram 14 row- address mux control logic column- address counter/ latch mode registers 11 command decode a0Ca13, ba0, ba1 14 address register 16 512 (x16) 8,192 i/o gating dm mask logic column decoder bank0 memory array (16,384 x 512 x 16) bank0 row- address latch and decoder 16,384 sense amplifiers bank control logic 16 bank1 bank2 bank3 14 9 2 2 refresh counter 4 4 4 2 rcvrs 16 16 16 ck out data dqs, dqs# internal ck, ck# ck, ck# col0, col1 col0, col1 ck in drvrs dll mux dqs generator 4 4 4 4 4 dq0Cdq3 dqs, dqs# 2 read latch write fifo and drivers data 4 4 4 4 16 1 1 1 1 mask 1 1 1 1 1 4 4 4 2 bank1 bank2 bank3 input registers dm ras# cas# ck cs# we# ck# cke odt vddq r1 r1 r2 r2 sw1 sw2 vssq sw1 sw2 odt control sw3 r3 r3 sw3 r1 r1 r2 r2 sw1 sw2 r3 r3 sw3 r1 r1 r2 r2 sw1 sw2 r3 r3 sw3 512mb: x4, x8, x16 ddr2 sdram functional block diagrams pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 4: 64 meg x 8 functional block diagram 14 row- address mux control logic column- address counter/ latch mode registers 10 command decode a0Ca13, ba0, ba1 14 address register 16 256 (x32) 8,192 i/o gating dm mask logic column decoder bank 0 memory array (16,384 x 256 x 32) bank 0 row- address latch and decoder 16,384 sense amplifiers bank control logic 16 bank 1 bank 2 bank 3 14 8 2 2 refresh counter 8 8 8 2 rcvrs 32 32 32 ck out data dqs, dqs# internal ck, ck# ck, ck# col0, col1 col0, col1 ck in drvrs dll mux dqs generator 8 8 8 8 8 dq0Cdq7 dqs, dqs# 2 read latch write fifo and drivers data 8 8 8 8 32 1 1 1 1 mask 1 1 1 1 1 4 8 8 2 bank 1 bank 2 bank 3 input registers dm rdqs# ras# cas# ck cs# we# ck# cke odt rdqs vddq r1 r1 r2 r2 sw1 sw2 vssq sw1 sw2 odt control sw3 r3 r3 sw3 r1 r1 r2 r2 sw1 sw2 r3 r3 sw3 r1 r1 r2 r2 sw1 sw2 r3 r3 sw3 figure 5: 32 meg x 16 functional block diagram 13 row- address mux control logic column- address counter/ latch mode registers 10 a0Ca12, ba0, ba1 13 address register 15 256 (x64) 16,384 i/o gating dm mask logic column decoder bank 0 memory array (8,192 x 256 x 64) bank 0 row- address latch and decoder 8,192 sense amplifiers bank control logic 15 bank 1 bank 2 bank 3 13 8 2 2 refresh counter 16 16 16 4 64 64 64 ck out data udqs, udqs# ldqs, ldqs# internal ck, ck# ck, ck# col0, col1 col0, col1 ck in dll mux dqs generator 16 16 16 16 16 udqs, udqs# ldqs, ldqs# 4 read latch write fifo and drivers data 16 16 16 16 64 2 2 2 2 mask 2 2 2 2 2 8 16 16 2 bank 1 bank 2 bank 3 input registers udm, ldm dq0Cdq15 ras# cas# ck cs# we# ck# command decode cke odt drvrs rcvrs vddq r1 r1 r2 r2 sw1 sw2 vssq sw1 sw2 odt control sw3 r3 r3 sw3 r1 r1 r2 r2 sw1 sw2 r3 r3 sw3 r1 r1 r2 r2 sw1 sw2 r3 r3 sw3 512mb: x4, x8, x16 ddr2 sdram functional block diagrams pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. ball assignments and descriptions figure 6: 60-ball fbga C x4, x8 ball assignments (top view) 1 2 3 4 6 7 8 9 5 v dd n f , dq6 v ddq n f , dq4 v ddl rfu v ss v dd n f , rdqs#/nu v ssq dq1 v ssq v ref cke ba0 a10 a3 a7 a12 v ss dm, dm/rdqs v ddq dq3 v ss we# ba1 a1 a5 a9 rfu v ssq dqs v ddq dq2 v ssdl ras# cas# a2 a6 a11 rfu v ddq n f , dq7 v ddq n f , dq5 v dd odt v dd v ss dqs#/nu v ssq dq0 v ssq ck ck# cs# a0 a4 a8 a13 a b c d e f g h j k l 512mb: x4, x8, x16 ddr2 sdram ball assignments and descriptions pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 7: 84-ball fbga C x16 ball assignments (top view) 1 2 3 4 6 7 8 9 5 v dd dq14 v ddq dq12 v dd dq6 v ddq dq4 v ddl rfu v ss v dd nc v ssq dq9 v ssq nc v ssq dq1 v ssq v ref cke ba0 a10 a3 a7 a12 v ss udm v ddq dq11 v ss ldm v ddq dq3 v ss we# ba1 a1 a5 a9 rfu v ssq udqs v ddq dq10 v ssq ldqs v ddq dq2 v ssdl ras# cas# a2 a6 a11 rfu v ddq dq15 v ddq dq13 v ddq dq7 v ddq dq5 v dd odt v dd v ss udqs#/nu v ssq dq8 v ssq ldqs#/nu v ssq dq0 v ssq ck ck# cs# a0 a4 a8 rfu a b c d e f g h j k l m n p r 512mb: x4, x8, x16 ddr2 sdram ball assignments and descriptions pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 3: fbga 84-ball C x16 and 60-ball C x4, x8 descriptions symbol type description a[12:0] (x16) a[13:0] (x4, x8) input address inputs: provide the row address for activate commands, and the column ad- dress and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge com- mand determines whether the precharge applies to one bank (a10 low, bank selected by ba[1:0]) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. ba0, ba1 input bank address inputs: ba[1:0] define to which bank an activate, read, write, or pre- charge command is being applied. ba[1:0] define which mode register including mr, emr, emr(2), and emr(3) is loaded during the load mode command. ck, ck# input clock: ck and ck# are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. output data (dq and dqs/dqs#) is referenced to the crossings of ck and ck#. cke input clock enable: cke (registered high) activates and cke (registered low) deactivates clocking circuitry on the ddr2 sdram. the specific circuitry that is enabled/disabled is dependent on the ddr2 sdram configuration and operating mode. cke low provides precharge power-down and self refresh operations (all banks idle), or activate power- down (row active in any bank). cke is synchronous for power-down entry, power-down exit, output disable, and for self refresh entry. cke is asynchronous for self refresh exit. input buffers (excluding ck, ck#, cke, and odt) are disabled during power- down. input buffers (excluding cke) are disabled during self refresh. cke is an sstl_18 input but will detect a lvcmos low level once v dd is applied during first power- up. after v ref has become stable during the power-on and initialization sequence, it must be maintained for proper operation of the cke receiver. for proper self-refresh operation, v ref must be maintained. cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for exter- nal bank selection on systems with multiple ranks. cs# is considered part of the com- mand code. ldm, udm, dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm balls are input-only, the dm loading is designed to match that of dq and dqs balls. ldm is dm for lower byte dq[7:0] and udm is dm for upper byte dq[15:8]. odt input on-die termination: odt (registered high) enables termination resistance internal to the ddr2 sdram. when enabled, odt is only applied to each of the following balls: dq[15:0], ldm, udm, ldqs, ldqs#, udqs, and udqs# for the x16; dq[7:0], dqs, dqs#, rdqs, rdqs#, and dm for the x8; dq[3:0], dqs, dqs#, and dm for the x4. the odt input will be ignored if disabled via the load mode command. ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. dq[15:0] (x16) dq[3:0] (x4) dq[7:0] (x8) i/o data input/output: bidirectional data bus for 32 meg x 16. bidirectional data bus for 128 meg x 4. bidirectional data bus for 64 meg x 8. 512mb: x4, x8, x16 ddr2 sdram ball assignments and descriptions pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 3: fbga 84-ball C x16 and 60-ball C x4, x8 descriptions (continued) symbol type description dqs, dqs# i/o data strobe: output with read data, input with write data for source synchronous oper- ation. edge-aligned with read data, center-aligned with write data. dqs# is only used when differential data strobe mode is enabled via the load mode command. ldqs, ldqs# i/o data strobe for lower byte: output with read data, input with write data for source synchronous operation. edge-aligned with read data, center-aligned with write data. ldqs# is only used when differential data strobe mode is enabled via the load mode command. udqs, udqs# i/o data strobe for upper byte: output with read data, input with write data for source synchronous operation. edge-aligned with read data, center-aligned with write data. udqs# is only used when differential data strobe mode is enabled via the load mode command. rdqs, rdqs# output redundant data strobe: for 64 meg x 8 only. rdqs is enabled/disabled via the load mode command to the extended mode register (emr). when rdqs is enabled, rdqs is output with read data only and is ignored during write data. when rdqs is disabled, ball b3 becomes data mask (see dm ball). rdqs# is only used when rdqs is enabled and dif- ferential data strobe mode is enabled. v dd supply power supply: 1.8v 0.1v. v ddq supply dq power supply: 1.8v 0.1v. isolated on the device for improved noise immunity. v ddl supply dll power supply: 1.8v 0.1v. v ref supply sstl_18 reference voltage (v ddq /2). v ss supply ground. v ssdl supply dll ground: isolated on the device from v ss and v ssq . v ssq supply dq ground: isolated on the device for improved noise immunity. nc C no connect: these balls should be left unconnected. nf C no function: x8: these balls are used as dq[7:4]; x4: they are no function. nu C not used: if emr(e10) = 0: x16, a8 = udqs# and e8 = ldqs#; x8, a2 = rdqs# and a8 = dqs#; x4, a2 = nu and a8 = nu. if emr(e10) = 1: x16, a8 = nu and e8 = nu; x8, a2 = nu and a8 = nu; x4, a2 = nu and a8 = nu. rfu C reserved for future use: bank address ba2, row address bits a13 (x16 only), a14, and a15. 512mb: x4, x8, x16 ddr2 sdram ball assignments and descriptions pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. packaging package dimensions figure 8: 84-ball fbga (8mm x 12.5mm) C x16 ball a1 id 1.2 max 8 0.1 ball a1 id 84x ?0.45 solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu) . dimensions apply to solder balls post-reflow on ?0.35 smd ball pads. 0.8 typ 11.2 ctr 12.5 0.1 0.8 0.05 0.12 a a seating plane 6.4 ctr 0.8 typ 0.25 min 1.8 ctr nonconductive overmold 0.155 9 8 7 3 2 1 a b c d e f g h j k l m n p r notes: 1. all dimensions are in millimeters. 2. solder ball material for this package is also available as leaded eutectic (62% sn, 36% pb, 2% ag). 512mb: x4, x8, x16 ddr2 sdram packaging pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 9: 60-ball fbga (8mm x 10mm) C x4, x8 ball a1 id 1.2 max 0.25 min 8 0.1 ball a1 id 60x ?0.45 solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu). dimensions apply to solder balls post-reflow on ?0.35 smd ball pads. 0.8 typ 0.8 typ 8 ctr 10 0.1 0.8 0.05 0.12 a a seating plane 6.4 ctr 9 8 7 3 2 1 a b c d e f g h j k l 1.8 ctr nonconductive overmold 0.155 notes: 1. all dimensions are in millimeters. 2. solder ball material for this package is also available as leaded eutectic (62% sn, 36% pb, 2% ag). 512mb: x4, x8, x16 ddr2 sdram packaging pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. fbga package capacitance table 4: input capacitance parameter symbol min max units notes input capacitance: ck, ck# c ck 1.0 2.0 pf 1 delta input capacitance: ck, ck# c dck C 0.25 pf 2, 3 input capacitance: address balls, bank address balls, cs#, ras#, cas#, we#, cke, odt c i 1.0 2.0 pf 1, 4 delta input capacitance: address balls, bank address balls, cs#, ras#, cas#, we#, cke, odt c di C 0.25 pf 2, 3 input/output capacitance: dq, dqs, dm, nf c io 2.5 4.0 pf 1, 5 delta input/output capacitance: dq, dqs, dm, nf c dio C 0.5 pf 2, 3 notes: 1. this parameter is sampled. v dd = +1.8v 0.1v, v ddq = +1.8v 0.1v, v ref = v ss , f = 100 mhz, t c = 25c, v out(dc) = v ddq /2, v out (peak-to-peak) = 0.1v. dm input is grouped with i/o balls, reflecting the fact that they are matched in loading. 2. the capacitance per ball group will not differ by more than this maximum amount for any given device. 3. c are not pass/fail parameters; they are targets. 4. reduce max limit by 0.25pf for -25 and -25e speed devices. 5. reduce max limit by 0.5pf for -3, -3e, -5e, -25, -25e, and -37e speed devices. 512mb: x4, x8, x16 ddr2 sdram packaging pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. electrical specifications C absolute ratings stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions oustide those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. table 5: absolute maximum dc ratings parameter symbol min max units notes v dd supply voltage relative to v ss v dd C1.0 2.3 v 1 v ddq supply voltage relative to v ssq v ddq C0.5 2.3 v 1, 2 v ddl supply voltage relative to v ssl v ddl C0.5 2.3 v 1 voltage on any ball relative to v ss v in , v out C0.5 2.3 v 3 input leakage current; any input 0v v in v dd ; all other balls not under test = 0v i i C5 5 a output leakage current; 0v v out v ddq ; dq and odt disabled i oz C5 5 a v ref leakage current; v ref = valid v ref level i vref C2 2 a notes: 1. v dd , v ddq , and v ddl must be within 300mv of each other at all times; this is not re- quired when power is ramping down. 2. v ref 0.6 x v ddq ; however, v ref may be v ddq provided that v ref 300mv. 3. voltage on any i/o may not exceed voltage on v ddq . temperature and thermal impedance it is imperative that the ddr2 sdram devices temperature specifications, shown in table 6 (page 22), be maintained in order to ensure the junction temperature is in the proper operating range to meet data sheet specifications. an important step in maintain- ing the proper junction temperature is using the devices thermal impedances correct- ly. the thermal impedances are listed in table 7 (page 22) for the applicable and available die revision and packages. incorrectly using thermal impedances can produce significant errors. read micron tech- nical note tn-00-08, thermal applications, prior to using the thermal impedances listed in table 7. for designs that are expected to last several years and require the flexi- bility to use several dram die shrinks, consider using final target theta values (rather than existing values) to account for increased thermal impedances from the die size re- duction. the ddr2 sdram devices safe junction temperature range can be maintained when the t c specification is not exceeded. in applications where the devices ambient temper- ature is too high, use of forced air and/or heat sinks may be required in order to satisfy the case temperature specifications. 512mb: x4, x8, x16 ddr2 sdram electrical specifications C absolute ratings pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 6: temperature limits parameter symbol min max units notes storage temperature t stg C55 150 c 1 operating temperature: commercial t c 0 85 c 2, 3 operating temperature: industrial t c C40 95 c 2, 3 , 4 t a C40 85 c 4, 5 operating temperature: automotive t c C40 105 c 2, 3, 4 t a C40 105 c 4, 5 notes: 1. max storage case temperature t stg is measured in the center of the package, as shown in figure 10. this case temperature limit is allowed to be exceeded briefly during pack- age reflow, as noted in micron technical note tn-00-15, recommended soldering parameters. 2. max operating case temperature t c is measured in the center of the package, as shown in figure 10. 3. device functionality is not guaranteed if the device exceeds maximum t c during operation. 4. both temperature specifications must be satisfied. 5. operating ambient temperature surrounding the package. figure 10: example temperature test point location width (w) 0.5 (w) length (l) 0.5 (l) test point lmm x wmm fbga table 7: thermal impedance die revision package substrate ja (c/w) airflow = 0m/s ja (c/w) airflow = 1m/s ja (c/w) airflow = 2m/s jb (c/w) jc (c/w) f 1 60-ball 2-layer 71.4 54.1 47.5 33.7 5.5 4-layer 53.6 44.5 40.5 33.5 84-ball 2-layer 65.8 50.4 44.3 30.7 4.1 4-layer 50.0 41.3 37.7 30.5 512mb: x4, x8, x16 ddr2 sdram electrical specifications C absolute ratings pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 7: thermal impedance (continued) die revision package substrate ja (c/w) airflow = 0m/s ja (c/w) airflow = 1m/s ja (c/w) airflow = 2m/s jb (c/w) jc (c/w) g 1 60-ball 2-layer 94.2 76.5 70.1 57.3 6.1 4-layer 76.4 66.9 63.1 56.5 84-ball 2-layer 88.8 71.3 65.6 52.5 6.0 4-layer 71.4 62.1 58.7 52.0 note: 1. thermal resistance data is based on a number of samples from multiple lots and should be viewed as a typical number. 512mb: x4, x8, x16 ddr2 sdram electrical specifications C absolute ratings pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. electrical specifications C i dd parameters i dd specifications and conditions table 8: general i dd parameters i dd parameters -187e -25e -25 -3e -3 -37e -5e units cl (i dd ) 7 5 6 4 5 4 3 t ck t rcd (i dd ) 13.125 12.5 15 12 15 15 15 ns t rc (i dd ) 58.125 57.5 60 57 60 60 55 ns t rrd (i dd ) - x4/x8 (1kb) 7.5 7.5 7.5 7.5 7.5 7.5 7.5 ns t rrd (i dd ) - x16 (2kb) 10 10 10 10 10 10 10 ns t ck (i dd ) 1.875 2.5 2.5 3 3 3.75 5 ns t ras min (i dd ) 45 45 45 45 45 45 40 ns t ras max (i dd ) 70,000 70,000 70,000 70,000 70,000 70,000 70,000 ns t rp (i dd ) 13.125 12.5 15 12 15 15 15 ns t rfc (i dd - 256mb) 75 75 75 75 75 75 75 ns t rfc (i dd - 512mb) 105 105 105 105 105 105 105 ns t rfc (i dd - 1gb) 127.5 127.5 127.5 127.5 127.5 127.5 127.5 ns t rfc (i dd - 2gb) 197.5 197.5 197.5 197.5 197.5 197.5 197.5 ns t faw (i dd ) - x4/x8 (1kb) defined by pattern in on page ns t faw (i dd ) - x16 (2kb) defined by pattern in on page ns i dd7 conditions the detailed timings are shown below for i dd7 . where general i dd parameters in the general parameters table conflict with pattern requirements in the i dd7 timing pat- terns table, then the i dd7 timing patterns requirements take precedence. table 9: i dd7 timing patterns (4-bank interleave read operation) speed grade i dd7 timing patterns timing patterns for 4-bank x4/x8/x16 devices -5e a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d -37e a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d -3 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d -3e a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d -25 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d d d d d -25e a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d d d d -187e a0 ra0 d d d d a1 ra1 d d d d a2 ra2 d d d d a3 ra3 d d d d d d d d d d d notes: 1. a = active; ra = read auto precharge; d = deselect. 2. all banks are being interleaved at t rc (i dd ) without violating t rrd (i dd ) using a bl = 4. 3. control and address bus inputs are stable during deselects. 512mb: x4, x8, x16 ddr2 sdram electrical specifications C i dd parameters pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 10: ddr2 i dd specifications and conditions (die revision f) notes: 1C7 apply to the entire table parameter/condition symbol configuration -25e/ -25 -3e/-3 -37e -5e units operating one bank active-precharge current : t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd0 x4, x8 100 90 80 80 ma x16 135 120 110 110 operating one bank active-read-pre- charge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid com- mands; address bus inputs are switching; da- ta pattern is same as i dd4w i dd1 x4, x8 115 105 95 90 ma x16 165 150 135 130 precharge power-down current: all banks idle; t ck = t ck (i dd ); cke is low; other con- trol and address bus inputs are stable; data bus inputs are floating i dd2p x4, x8, x16 7 7 7 7 ma precharge quiet standby current: all banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are floating i dd2q x4, x8 50 45 40 35 ma x16 65 55 45 40 precharge standby current: all banks idle; t ck = t ck (i dd ); cke is high, cs# is high; oth- er control and address bus inputs are switch- ing; data bus inputs are switching i dd2n x4, x8 55 50 45 40 ma x16 70 60 50 45 active power-down current: all banks open; t ck = t ck (i dd ); cke is low; other con- trol and address bus inputs are stable; data bus inputs are floating i dd3pf fast pdn exit mr12 = 0 40 35 30 25 ma i dd3ps slow pdn exit mr12 = 1 12 12 12 12 active standby current: all banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd3n x4, x8 70 65 55 45 ma x16 75 70 60 50 operating burst write current: all banks open, continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4w x4, x8 195 170 140 115 ma x16 295 250 205 160 512mb: x4, x8, x16 ddr2 sdram electrical specifications C i dd parameters pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 10: ddr2 i dd specifications and conditions (die revision f) (continued) notes: 1C7 apply to the entire table parameter/condition symbol configuration -25e/ -25 -3e/-3 -37e -5e units operating burst read current: all banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus in- puts are switching i dd4r x4, x8 205 180 145 115 ma x16 275 235 195 155 burst refresh current: t ck = t ck (i dd ); re- fresh command at every t rfc (i dd ) interval; cke is high, cs# is high between valid com- mands; other control and address bus inputs are switching; data bus inputs are switching i dd5 x4, x8 230 180 170 165 ma x16 230 185 175 170 self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus in- puts are floating; data bus inputs are floating i dd6 x4, x8, x16 7 7 7 7 ma i dd6l 3 3 3 3 operating bank interleave read current: all bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching; see i dd7 conditions (page 24) for details i dd7 x4, x8 300 240 225 220 ma x16 370 350 340 340 notes: 1. i dd specifications are tested after the device is properly initialized. 0c t c +85c. 2. v dd = +1.8v 0.1v, v ddq = +1.8v 0.1v, v ddl = +1.8v 0.1v, v ref = v ddq /2. 3. i dd parameters are specified with odt disabled. 4. data bus consists of dq, dm, dqs, dqs#, rdqs, rdqs#, ldqs, ldqs#, udqs, and udqs#. i dd values must be met with all combinations of emr bits 10 and 11. 5. definitions for i dd conditions: low v in v il(ac)max high v in v ih(ac)min stable inputs stable at a high or low level floating inputs at v ref = v ddq /2 switching inputs changing between high and low every other clock cycle (once per two clocks) for address and control signals switching inputs changing between high and low every other data transfer (once per clock) for dq signals, not including masks or strobes 6. i dd1 , i dd4r , and i dd7 require a12 in emr1 to be enabled during testing. 7. the following i dd values must be derated (i dd limits increase) on it-option or on at-op- tion devices when operated outside of the range 0c t c 85c: 512mb: x4, x8, x16 ddr2 sdram electrical specifications C i dd parameters pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. when t c 0c i dd2p and i dd3p(slow) must be derated by 4%; i dd4r and i dd5w must be derat- ed by 2%; and i dd6 and i dd7 must be derated by 7% when t c 85c i dd0 , i dd1 , i dd2n , i dd2q , i dd3n , i dd3p(fast) , i dd4r , i dd4w , and i dd5w must be derat- ed by 2%; i dd2p must be derated by 20%; i dd3p slow must be derated by 30%; and i dd6 must be derated by 80% (i dd6 will increase by this amount if t c < 85c and the 2x refresh option is still enabled) 512mb: x4, x8, x16 ddr2 sdram electrical specifications C i dd parameters pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 27 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 11: ddr2 i dd specifications and conditions (die revision g) notes: 1C7 apply to the entire table parameter/condition symbol configura- tion -187e -25e/ -25 -3e/-3 -37e -5e units operating one bank active-pre- charge current : t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, cs# is high between valid com- mands; address bus inputs are switch- ing; data bus inputs are switching i dd0 x4, x8 tbd 65 60 55 55 ma x16 tbd 80 75 70 70 operating one bank active-read- precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; ad- dress bus inputs are switching; data pattern is same as i dd4w i dd1 x4, x8 tbd 75 70 65 65 ma x16 tbd 95 90 85 85 precharge power-down current: all banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating i dd2p x4, x8, x16 tbd 7 7 7 7 ma precharge quiet standby current: all banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are floating i dd2q x4, x8 tbd 24 22 20 19 ma x16 tbd 26 24 22 20 precharge standby current: all banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus inputs are switching; da- ta bus inputs are switching i dd2n x4, x8 tbd 28 25 23 21 ma x16 tbd 30 27 25 23 active power-down current: all banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating i dd3pf fast pdn exit mr12 = 0 tbd 18 15 14 13 ma i dd3ps slow pdn exit mr12 = 1 tbd 9 9 9 9 active standby current: all banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid com- mands; other control and address bus inputs are switching; data bus inputs are switching i dd3n x4, x8 tbd 33 30 27 24 ma x16 tbd 35 32 29 26 512mb: x4, x8, x16 ddr2 sdram electrical specifications C i dd parameters pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 28 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 11: ddr2 i dd specifications and conditions (die revision g) (continued) notes: 1C7 apply to the entire table parameter/condition symbol configura- tion -187e -25e/ -25 -3e/-3 -37e -5e units operating burst write current: all banks open, continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high be- tween valid commands; address bus inputs are switching; data bus inputs are switching i dd4w x4, x8 tbd 125 115 99 85 ma x16 tbd 160 135 120 105 operating burst read current: all banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between val- id commands; address bus inputs are switching; data bus inputs are switch- ing i dd4r x4, x8 tbd 120 110 95 80 ma x16 tbd 150 125 110 95 burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, cs# is high between valid commands; oth- er control and address bus inputs are switching; data bus inputs are switch- ing i dd5 x4, x8 tbd 95 90 90 87 ma x16 tbd 100 90 90 87 self refresh current: ck and ck# at 0v; cke 0.2v; other control and ad- dress bus inputs are floating; data bus inputs are floating i dd6 x4, x8, x16 tbd 7 7 7 7 ma i dd6l tbd 3 3 3 3 operating bank interleave read current: all bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switch- ing; see i dd7 conditions (page 24) for details i dd7 x4, x8 tbd 150 140 135 130 ma x16 tbd 215 200 195 190 notes: 1. i dd specifications are tested after the device is properly initialized. 0c t c +85c. 2. v dd = +1.8v 0.1v, v ddq = +1.8v 0.1v, v ddl = +1.8v 0.1v, v ref = v ddq /2. 3. i dd parameters are specified with odt disabled. 4. data bus consists of dq, dm, dqs, dqs#, rdqs, rdqs#, ldqs, ldqs#, udqs, and udqs#. i dd values must be met with all combinations of emr bits 10 and 11. 512mb: x4, x8, x16 ddr2 sdram electrical specifications C i dd parameters pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 29 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. 5. definitions for i dd conditions: low v in v il(ac)max high v in v ih(ac)min stable inputs stable at a high or low level floating inputs at v ref = v ddq /2 switching inputs changing between high and low every other clock cycle (once per two clocks) for address and control signals switching inputs changing between high and low every other data transfer (once per clock) for dq signals, not including masks or strobes 6. i dd1 , i dd4r , and i dd7 require a12 in emr1 to be enabled during testing. 7. the following i dd values must be derated (i dd limits increase) on it-option or on at-op- tion devices when operated outside of the range 0c t c 85c: when t c 0c i dd2p and i dd3p(slow) must be derated by 4%; i dd4r and i dd5w must be derat- ed by 2%; and i dd6 and i dd7 must be derated by 7% when t c 85c i dd0 , i dd1 , i dd2n , i dd2q , i dd3n , i dd3p(fast) , i dd4r , i dd4w , and i dd5w must be derat- ed by 2%; i dd2p must be derated by 20%; i dd3p slow must be derated by 30%; and i dd6 must be derated by 80% (i dd6 will increase by this amount if t c < 85c and the 2x refresh option is still enabled) 512mb: x4, x8, x16 ddr2 sdram electrical specifications C i dd parameters pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 30 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. ac timing operating specifications table 12: ac operating specifications and conditions not all speed grades listed may be supported for this device; refer to the title page for speeds supported; notes: 1C5 apply to the entire table; v ddq = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -187e -25e -25 -3e -3 -37e -5e units notes parameter symbol min max min max min max min max min max min max min max clock clock cycle time cl = 7 t ck (avg) 1.875 8.0 C C C C C C C C C C C C ns 6, 7, 8, 9 cl = 6 t ck (avg) 2.5 8.0 2.5 8.0 2.5 8.0 C C C C C C C C cl = 5 t ck (avg) 3.0 8.0 2.5 8.0 3.0 8.0 3.0 8.0 3.0 8.0 C C C C cl = 4 t ck (avg) 3.75 8.0 3.75 8.0 3.75 8.0 3.0 8.0 3.75 8.0 3.75 8.0 5.0 8.0 cl = 3 t ck (avg) 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0 ck high-level width t ch (avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 t ck 10 ck low-level width t cl (avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 t ck half clock period t hp min = lesser of t ch and t cl max = n/a ps 11 absolute t ck t ck (abs) min = t ck (avg) min + t jitper (min) max = t ck (avg) max + t jitper (max) ps absolute ck high-level width t ch (abs) min = t ck (avg) min t ch (avg) min + t jitdty (min) max = t ck (avg) max t ch (avg) max + t jitdty (max) ps absolute ck low-level width t cl (abs) min = t ck (avg) min t cl (avg) min + t jitdty (min) max = t ck (avg) max t cl (avg) max + t jitdty (max) ps clock jitter period jitter t jitper C90 90 C100 100 C100 100 C125 125 C125 125 C125 125 C125 125 ps 12 half period t jitdty C75 75 C100 100 C100 100 C125 125 C125 125 C125 125 C150 150 ps 13 cycle to cycle t jitcc 180 200 200 250 250 250 250 ps 14 cumulative error, 2 cycles t err 2per C132 132 C150 150 C150 150 C175 175 C175 175 C175 175 C175 175 ps 15 cumulative error, 3 cycles t err 3per C157 157 C175 175 C175 175 C225 225 C225 225 C225 225 C225 225 ps 15 cumulative error, 4 cycles t err 4per C175 175 C200 200 C200 200 C250 250 C250 250 C250 250 C250 250 ps 15 cumulative error, 5 cycles t err 5per C188 188 C200 200 C200 200 C250 250 C250 250 C250 250 C250 250 ps 15, 16 cumulative error, 6C10 cycles t err 6C 10per C250 250 C300 300 C300 300 C350 350 C350 350 C350 350 C350 350 ps 15, 16 cumulative error, 11C50 cycles t err 11C 50per C425 425 C450 450 C450 450 C450 450 C450 450 C450 450 C450 450 ps 15 512mb: x4, x8, x16 ddr2 sdram ac timing operating specifications pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 31 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 12: ac operating specifications and conditions (continued) not all speed grades listed may be supported for this device; refer to the title page for speeds supported; notes: 1C5 apply to the entire table; v ddq = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -187e -25e -25 -3e -3 -37e -5e units notes parameter symbol min max min max min max min max min max min max min max data strobe-out dqs output access time from ck/ck# t dqsck C300 +300 C350 +350 C350 +350 C400 +400 C400 +400 C450 +450 C500 +500 ps 19 dqs read preamble t rpre min = 0.9 t ck max = 1.1 t ck t ck 17, 18, 19 dqs read postamble t rpst min = 0.4 t ck max = 0.6 t ck t ck 17, 18, 19, 20 ck/ck# to dqs low-z t lz 1 min = t ac (min) max = t ac (max) ps 19, 21, 22 data strobe-in dqs rising edge to ck rising edge t dqss min = C0.25 t ck max = +0.25 t ck t ck 18 dqs input-high pulse width t dqsh min = 0.35 t ck max = n/a t ck 18 dqs input-low pulse width t dqsl min = 0.35 t ck max = n/a t ck 18 dqs falling to ck rising: setup time t dss min = 0.2 t ck max = n/a t ck 18 dqs falling from ck rising: hold time t dsh min = 0.2 t ck max = n/a t ck 18 write preamble setup time t wpres min = 0 max = n/a ps 23, 24 dqs write preamble t wpre min = 0.35 t ck max = n/a t ck 18 dqs write postamble t wpst min = 0.4 t ck max = 0.6 t ck t ck 18, 25 write command to first dqs transition C min = wl - t dqss max = wl + t dqss t ck 512mb: x4, x8, x16 ddr2 sdram ac timing operating specifications pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 32 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 12: ac operating specifications and conditions (continued) not all speed grades listed may be supported for this device; refer to the title page for speeds supported; notes: 1C5 apply to the entire table; v ddq = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -187e -25e -25 -3e -3 -37e -5e units notes parameter symbol min max min max min max min max min max min max min max data-out dq output access time from ck/ck# t ac C350 +350 C400 +400 C400 +400 C450 +450 C450 +450 C500 +500 C600 +600 ps 19 dqsCdq skew, dqs to last dq valid, per group, per access t dqsq C 175 C 200 C 200 C 240 C 240 C 300 C 350 ps 26, 27 dq hold from next dqs strobe t qhs C 250 C 300 C 300 C 340 C 340 C 400 C 450 ps 28 dqCdqs hold, dqs to first dq not valid t qh min = t hp - t qhs max = n/a ps 26, 27, 28 ck/ck# to dq, dqs high-z t hz min = n/a max = t ac (max) ps 19, 21, 29 ck/ck# to dq low-z t lz 2 min = 2 t ac (min) max = t ac (max) ps 19, 21, 22 data valid output window dvw min = t qh - t dqsq max = n/a ns 26, 27 data-in dq and dm input setup time to dqs t dsb 0 C 50 C 50 C 100 C 100 C 100 C 150 C ps 26, 30, 31 dq and dm input hold time to dqs t dhb 75 C 125 C 125 C 175 C 175 C 225 C 275 C ps 26, 30, 31 dq and dm input setup time to dqs t dsa 200 C 250 C 250 C 300 C 300 C 350 C 400 C ps 26, 30, 31 dq and dm input hold time to dqs t dha 200 C 250 C 250 C 300 C 300 C 350 C 400 C ps 26, 30, 31 dq and dm input pulse width t dipw min = 0.35 t ck max = n/a t ck 18, 32 512mb: x4, x8, x16 ddr2 sdram ac timing operating specifications pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 33 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 12: ac operating specifications and conditions (continued) not all speed grades listed may be supported for this device; refer to the title page for speeds supported; notes: 1C5 apply to the entire table; v ddq = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -187e -25e -25 -3e -3 -37e -5e units notes parameter symbol min max min max min max min max min max min max min max command and address input setup time t isb 125 C 175 C 175 C 200 C 200 C 250 C 350 C ps 31, 33 input hold time t ihb 200 C 250 C 250 C 275 C 275 C 375 C 475 C ps 31, 33 input setup time t isa 325 C 375 C 375 C 400 C 400 C 500 C 600 C ps 31, 33 input hold time t iha 325 C 375 C 375 C 400 C 400 C 500 C 600 C ps 31, 33 input pulse width t ipw 0.6 C 0.6 C 0.6 C 0.6 C 0.6 C 0.6 C 0.6 C t ck 18, 32 activate-to- activate delay, same bank t rc 54 C 55 C 55 C 54 C 55 C 55 C 55 C ns 18, 34 activate-to-read or write delay t rcd 13.125 C 12.5 C 15 C 12 C 15 C 15 C 15 C ns 18 activate-to- precharge delay t ras 40 70k 40 70k 40 70k 40 70k 40 70k 40 70k 40 70k ns 18, 34, 35 precharge period t rp 13.125 C 12.5 C 15 C 12 C 15 C 15 C 15 C ns 18, 36 pre- charge all period <1gb t rpa 13.125 C 12.5 C 15 C 12 C 15 C 15 C 15 C ns 18, 36 1gb t rpa 15 C 15 C 17.5 15 18 18.75 20 ns 18, 36 activate -to- activate delay different bank x4, x8 t rrd 7.5 C 7.5 C 7.5 C 7.5 C 7.5 C 7.5 C 7.5 C ns 18, 37 x16 t rrd 10 C 10 C 10 C 10 C 10 C 10 C 10 C ns 18, 37 4-bank activate period ( 1gb) x4, x8 t faw 35 C 35 C 35 C 37.5 C 37.5 C 37.5 C 37.5 C ns 18, 38 x16 t faw 45 C 45 C 45 C 50 C 50 C 50 C 50 C ns 18, 38 512mb: x4, x8, x16 ddr2 sdram ac timing operating specifications pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 34 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 12: ac operating specifications and conditions (continued) not all speed grades listed may be supported for this device; refer to the title page for speeds supported; notes: 1C5 apply to the entire table; v ddq = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -187e -25e -25 -3e -3 -37e -5e units notes parameter symbol min max min max min max min max min max min max min max command and address internal read-to- precharge delay t rtp 7.5 C 7.5 C 7.5 C 7.5 C 7.5 C 7.5 C 7.5 C ns 18, 37, 39 cas#-to-cas# delay t ccd 2 C 2 C 2 C 2 C 2 C 2 C 2 C t ck 18 write recovery time t wr 15 C 15 C 15 C 15 C 15 C 15 C 15 C ns 18, 37 write ap recovery + precharge time t dal t wr + t rp C t wr + t rp C t wr + t rp C t wr + t rp C t wr + t rp C t wr + t rp C t wr + t rp C ns 40 internal write-to- read delay t wtr 7.5 C 7.5 C 7.5 C 7.5 C 7.5 C 7.5 C 10 C ns 18, 37 load mode cycle time t mrd 2 C 2 C 2 C 2 C 2 C 2 C 2 C t ck 18 refresh refresh- to- activate or to -refresh interval 256mb t rfc 75 C 75 C 75 C 75 C 75 C 75 C 75 C ns 18, 41 512mb 105 C 105 C 105 C 105 C 105 C 105 C 105 C 1gb 127.5 C 127.5 C 127.5 C 127.5 C 127.5 C 127.5 C 127.5 C 2gb 195 C 195 C 195 C 195 C 195 C 195 C 195 C average periodic refresh (commercial) t refi C 7.8 C 7.8 C 7.8 C 7.8 C 7.8 C 7.8 C 7.8 s 18, 41 average periodic refresh (industrial) t refi it C 3.9 C 3.9 C 3.9 C 3.9 C 3.9 C 3.9 C 3.9 s 18, 41 average periodic refresh (automotive) t refi at C 3.9 C 3.9 C 3.9 C 3.9 C 3.9 C 3.9 C 3.9 s 18, 41 cke low to ck, ck# uncertainty t delay min limit = t is + t ck + t ih max limit = n/a ns 42 512mb: x4, x8, x16 ddr2 sdram ac timing operating specifications pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 35 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 12: ac operating specifications and conditions (continued) not all speed grades listed may be supported for this device; refer to the title page for speeds supported; notes: 1C5 apply to the entire table; v ddq = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -187e -25e -25 -3e -3 -37e -5e units notes parameter symbol min max min max min max min max min max min max min max self refresh exit self refresh to nonread command t xsnr min limit = t rfc (min) + 10 max limit = n/a ns exit self refresh to read command t xsrd min limit = 200 max limit = n/a t ck 18 exit self refresh timing reference t isxr min limit = t is max limit = n/a ps 33, 43 power-down exit active power- down to read command mr12 = 0 t xard 3 C 2 C 2 C 2 C 2 C 2 C 2 C t ck 18 mr12 = 1 10 - al C 8 - al C 8 - al C 7 - al C 7 - al C 6 - al C 6 - al C t ck 18 exit precharge power-down and active power-down to any nonread command t xp 3 C 2 C 2 C 2 C 2 C 2 C 2 C t ck 18 cke min high/ low time t cke min = 3 max = n/a t ck 18, 44 512mb: x4, x8, x16 ddr2 sdram ac timing operating specifications pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 36 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 12: ac operating specifications and conditions (continued) not all speed grades listed may be supported for this device; refer to the title page for speeds supported; notes: 1C5 apply to the entire table; v ddq = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -187e -25e -25 -3e -3 -37e -5e units notes parameter symbol min max min max min max min max min max min max min max odt odt to power- down entry latency t anpd 4 C 3 C 3 C 3 C 3 C 3 C 3 C t ck 18 odt power-down exit latency t axpd 11 C 10 C 10 C 8 C 8 C 8 C 8 C t ck 18 odt turn-on delay t aond 2 t ck 18 odt turn-off delay t aofd 2.5 t ck 18, 45 odt turn-on t aon t ac (min) t ac (max) + 2,575 min = t ac (min) max = t ac (max) + 600 min = t ac (min) max = t ac (max) + 700 min = t ac (min) max = t ac (max) + 1,000 ps 19, 46 odt turn-off t aof min = t ac (min) max = t ac (max) + 600 ps 47, 48 odt turn-on (power-down mode) t aonpd t ac (min) + 2,000 2 t ck + t ac (max) + 1,000 min = t ac (min) + 2,000 max = 2 t ck + t ac (max) + 1,000 ps 49 odt turn-off (power-down mode) t aofpd min = t ac (min) + 2,000 max = 2.5 t ck + t ac (max) + 1,000 ps odt enable from mrs command t mod min = 12 max = n/a ns 18, 50 512mb: x4, x8, x16 ddr2 sdram ac timing operating specifications pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 37 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. notes: 1. all voltages are referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and the operation of the device are warranted for the full voltage range specified. odt is disabled for all measurements that are not odt-specific. 3. outputs measured with equivalent load (see figure 14 (page 48)). 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.0v in the test environment, and parameter specifica- tions are guaranteed for the specified ac input levels under normal use conditions. the slew rate for the input signals used to test the device is 1.0 v/ns for signals in the range between v il(ac) and v ih(ac) . slew rates other than 1.0 v/ns may require the timing parameters to be derated as specified. 5. the ac and dc input level specifications are as defined in the sstl_18 standard (that is, the receiver will effective- ly switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. ck and ck# input slew rate is referenced at 1 v/ns (2 v/ns if measured differentially). 7. operating frequency is only allowed to change during self refresh mode (see figure 77 (page 123)), precharge power-down mode, or system reset condition (see reset (page 124)). ssc allows for small deviations in operating frequency, provided the ssc guidelines are satisfied. 8. the clocks t ck (avg) is the average clock over any 200 consecutive clocks and t ck (avg) min is the smallest clock rate allowed (except for a deviation due to allowed clock jitter). input clock jitter is allowed provided it does not exceed values specified. also, the jitter must be of a random gaussian distribution in nature. 9. spread spectrum is not included in the jitter specification values. however, the input clock can accommodate spread spectrum at a sweep rate in the range 8C60 khz with an additional one percent t ck (avg); however, the spread spectrum may not use a clock rate below t ck (avg) min or above t ck (avg) max. 10. min ( t cl, t ch) refers to the smaller of the actual clock low time and the actual clock high time driven to the device. the clocks half period must also be of a gaussian distribution; t ch (avg) and t cl (avg) must be met with or without clock jitter and with or without duty cycle jitter. t ch (avg) and t cl (avg) are the average of any 200 consecutive ck falling edges. t ch limits may be exceeded if the duty cycle jitter is small enough that the absolute half period limits ( t ch [abs], t cl [abs]) are not violated. 11. t hp (min) is the lesser of t cl and t ch actually applied to the device ck and ck# inputs; thus, t hp (min) the lesser of t cl (abs) min and t ch (abs) min. 12. the period jitter ( t jitper) is the maximum deviation in the clock period from the average or nominal clock allowed in either the positive or negative direction. jedec specifies tighter jitter numbers during dll locking time. during dll lock time, the jitter values should be 20 percent less those than noted in the table (dll locked). 13. the half-period jitter ( t jitdty) applies to either the high pulse of clock or the low pulse of clock; however, the two cumulatively can not exceed t jitper. 14. the cycle-to-cycle jitter ( t jitcc) is the amount the clock period can deviate from one cycle to the next. jedec speci- fies tighter jitter numbers during dll locking time. during dll lock time, the jitter values should be 20 percent less than those noted in the table (dll locked). 15. the cumulative jitter error ( t err n per ), where n is 2, 3, 4, 5, 6C10, or 11C50 is the amount of clock time allowed to consecutively accumulate away from the average clock over any number of clock cycles. 16. jedec specifies using t err 6C10per when derating clock-related output timing (see notes 19 and 48). micron requires less derating by allowing t err 5per to be used. 17. this parameter is not referenced to a specific voltage level but is specified when the device output is no longer driving ( t rpst) or beginning to drive ( t rpre). 512mb: x4, x8, x16 ddr2 sdram ac timing operating specifications pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 38 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. 18. the inputs to the dram must be aligned to the associated clock, that is, the actual clock that latches it in. howev- er, the input timing (in ns) references to the t ck (avg) when determining the required number of clocks. the following input parameters are determined by taking the specified percentage times the t ck (avg) rather than t ck: t ipw, t dipw, t dqss, t dqsh, t dqsl, t dss, t dsh, t wpst, and t wpre. 19. the dram output timing is aligned to the nominal or average clock. most output parameters must be derated by the actual jitter error when input clock jitter is present; this will result in each parameter becoming larger. the following parameters are required to be derated by subtracting t err 5per (max): t ac (min), t dqsck (min), t lz dqs (min), t lz dq (min), t aon (min); while the following parameters are required to be derated by subtracting t err 5per (min): t ac (max), t dqsck (max), t hz (max), t lz dqs (max), t lz dq (max), t aon (max). the parameter t rpre (min) is derated by subtracting t jitper (max), while t rpre (max), is derated by subtracting t jitper (min). the parameter t rpst (min) is derated by subtracting t jitdty (max), while t rpst (max), is derated by subtracting t jitdty (min). output timings that require t err 5per derating can be observed to have offsets relative to the clock; however, the total window will not degrade. 20. when dqs is used single-ended, the minimum limit is reduced by 100ps. 21. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving ( t hz) or begins driv- ing ( t lz). 22. t lz (min) will prevail over a t dqsck (min) + t rpre (max) condition. 23. this is not a device limit. the device will operate with a negative value, but system performance could be degra- ded due to bus turnaround. 24. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 25. the intent of the dont care state after completion of the postamble is that the dqs-driven signal should either be high, low, or high-z, and that any signal transition within the input switching region must follow valid input requirements. that is, if dqs transitions high (above v ih[dc]min ), then it must not transition low (below v ih[dc] ) prior to t dqsh (min). 26. referenced to each output group: x4 = dqs with dq0Cdq3; x8 = dqs with dq0Cdq7; x16 = ldqs with dq0Cdq7; and udqs with dq8Cdq15. 27. the data valid window is derived by achieving other specifications: t hp ( t ck/2), t dqsq, and t qh ( t qh = t hp - t qhs). the data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. 28. t qh = t hp - t qhs; the worst case t qh would be the lesser of t cl (abs) max or t ch (abs) max times t ck (abs) min - t qhs. minimizing the amount of t ch (avg) offset and value of t jitdty will provide a larger t qh, which in turn will provide a larger valid data out window. 29. this maximum value is derived from the referenced test load. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. 30. the values listed are for the differential dqs strobe (dqs and dqs#) with a differential slew rate of 2 v/ns (1 v/ns for each signal). there are two sets of values listed: t ds a , t dh a and t ds b , t dh b . the t ds a , t dh a values (for reference only) are equivalent to the baseline values of t ds b , t dh b at v ref when the slew rate is 2 v/ns, differentially. the baseline values, t ds b , t dh b , are the jedec-defined values, referenced from the logic trip points. t ds b is referenced from v ih(ac) for a rising signal and v il(ac) for a falling signal, while t dh b is referenced from v il(dc) for a rising signal and v ih(dc) for a falling signal. if the differential dqs slew rate is not equal to 2 v/ns, then the baseline values must be derated by adding the values from table 31 (page 61) and table 32 (page 62). if the dqs differ- ential strobe feature is not enabled, then the dqs strobe is single-ended and the baseline values must be derated 512mb: x4, x8, x16 ddr2 sdram ac timing operating specifications pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 39 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. using table 33 (page 63). single-ended dqs data timing is referenced at dqs crossing v ref . the correct timing values for a single-ended dqs strobe are listed in table 34 (page 63)Ctable 36 (page 64) on table 34 (page 63), table 35 (page 64), and table 36 (page 64); listed values are already derated for slew rate varia- tions and converted from baseline values to v ref values. 31. v il /v ih ddr2 overshoot/undershoot. see ac overshoot/undershoot specification (page 54). 32. for each input signalnot the group collectively. 33. there are two sets of values listed for command/address: t is a , t ih a and t is b , t ih b . the t is a , t ih a values (for reference only) are equivalent to the baseline values of t is b , t ih b at v ref when the slew rate is 1 v/ns. the baseline values, t is b , t ih b , are the jedec-defined values, referenced from the logic trip points. t is b is referenced from v ih(ac) for a rising signal and v il(ac) for a falling signal, while t ih b is referenced from v il(dc) for a rising signal and v ih(dc) for a falling signal. if the command/address slew rate is not equal to 1 v/ns, then the baseline values must be derated by adding the values from table 29 (page 57) and table 30 (page 58). 34. this is applicable to read cycles only. write cycles generally require additional time due to t wr during auto pre- charge. 35. reads and writes with auto precharge are allowed to be issued before t ras (min) is satisfied because t ras lock- out feature is supported in ddr2 sdram. 36. when a single-bank precharge command is issued, t rp timing applies. t rpa timing applies when the pre- charge (all) command is issued, regardless of the number of banks open. for 8-bank devices ( 1gb), t rpa (min) = t rp (min) + t ck (avg) (table 12 (page 31) lists t rp [min] + t ck [avg] min). 37. this parameter has a two clock minimum requirement at any t ck. 38. the t faw (min) parameter applies to all 8-bank ddr2 devices. no more than four bank-activate commands may be issued in a given t faw (min) period. t rrd (min) restriction still applies. 39. the minimum internal read-to-precharge time. this is the time from which the last 4-bit prefetch begins to when the precharge command can be issued. a 4-bit prefetch is when the read command internally latches the read so that data will output cl later. this parameter is only applicable when t rtp/(2 t ck) > 1, such as frequen- cies faster than 533 mhz when t rtp = 7.5ns. if t rtp/(2 t ck) 1, then equation al + bl/2 applies. t ras (min) has to be satisfied as well. the ddr2 sdram will automatically delay the internal precharge command until t ras (min) has been satisfied. 40. t dal = ( n wr) + ( t rp/ t ck). each of these terms, if not already an integer, should be rounded up to the next integer. t ck refers to the application clock period; n wr refers to the t wr parameter stored in the mr9Cmr11. for exam- ple, -37e at t ck = 3.75ns with t wr programmed to four clocks would have t dal = 4 + (15ns/3.75ns) clocks = 4 + (4) clocks = 8 clocks. 41. the refresh period is 64ms (commercial) or 32ms (industrial and automotive). this equates to an average refresh rate of 7.8125s (commercial) or 3.9607s (industrial and automotive). to ensure all rows of all banks are properly refreshed, 8192 refresh commands must be issued every 64ms (commercial) or 32ms (industrial and automotive). the jedec t rfc max of 70,000ns is not required as bursting of auto refresh commands is allowed. 42. t delay is calculated from t is + t ck + t ih so that cke registration low is guaranteed prior to ck, ck# being re- moved in a system reset condition (see reset (page 124)). 43. t isxr is equal to t is and is used for cke setup time during self refresh exit, as shown in figure 67 (page 115). 44. t cke (min) of three clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the three clocks of registration. thus, after any cke transition, cke may not transition from its valid level during the time period of t is + 2 t ck + t ih. 512mb: x4, x8, x16 ddr2 sdram ac timing operating specifications pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 40 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. 45. the half-clock of t aofds 2.5 t ck assumes a 50/50 clock duty cycle. this half-clock value must be derated by the amount of half-clock duty cycle error. for example, if the clock duty cycle was 47/53, t aofd would actually be 2.5 - 0.03, or 2.47, for t aof (min) and 2.5 + 0.03, or 2.53, for t aof (max). 46. odt turn-on time t aon (min) is when the device leaves high-z and odt resistance begins to turn on. odt turn- on time t aon (max) is when the odt resistance is fully on. both are measured from t aond. 47. odt turn-off time t aof (min) is when the device starts to turn off odt resistance. odt turn off time t aof (max) is when the bus is in high-z. both are measured from t aofd. 48. half-clock output parameters must be derated by the actual t err 5per and t jitdty when input clock jitter is present; this will result in each parameter becoming larger. the parameter t aof (min) is required to be derated by subtract- ing both t err 5per (max) and t jitdty (max). the parameter t aof (max) is required to be derated by subtracting both t err 5per (min) and t jitdty (min). 49. the -187e maximum limit is 2 t ck + t ac (max) + 1000 but it will likely be 3 x t ck + t ac (max) + 1000 in the future. 50. should use 8 t ck for backward compatibility. 512mb: x4, x8, x16 ddr2 sdram ac timing operating specifications pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 41 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. ac and dc operating conditions table 13: recommended dc operating conditions (sstl_18) all voltages referenced to v ss parameter symbol min nom max units notes supply voltage v dd 1.7 1.8 1.9 v 1, 2 v ddl supply voltage v ddl 1.7 1.8 1.9 v 2, 3 i/o supply voltage v ddq 1.7 1.8 1.9 v 2, 3 i/o reference voltage v ref(dc) 0.49 v ddq 0.50 v ddq 0.51 v ddq v 4 i/o termination voltage (system) v tt v ref(dc) - 40 v ref(dc) v ref(dc) + 40 mv 5 notes: 1. v dd and v ddq must track each other. v ddq must be v dd . 2. v ssq = v ssl = v ss . 3. v ddq tracks with v dd ; v ddl tracks with v dd . 4. v ref is expected to equal v ddq /2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise (noncommon mode) on v ref may not exceed 1 percent of the dc value. peak-to-peak ac noise on v ref may not exceed 2 percent of v ref(dc) . this measurement is to be taken at the nearest v ref bypass capacitor. 5. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 512mb: x4, x8, x16 ddr2 sdram ac and dc operating conditions pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 42 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. odt dc electrical characteristics table 14: odt dc electrical characteristics all voltages are referenced to v ss parameter symbol min nom max units notes r tt effective impedance value for 75 setting emr (a6, a2) = 0, 1 r tt1(eff) 60 75 90 1, 2 r tt effective impedance value for 150 setting emr (a6, a2) = 1, 0 r tt2(eff) 120 150 180 1, 2 r tt effective impedance value for 50 setting emr (a6, a2) = 1, 1 r tt3(eff) 40 50 60 1, 2 deviation of vm with respect to v ddq /2 vm C6 C 6 % 3 notes: 1. r tt1(eff) and r tt2(eff) are determined by separately applying v ih(ac) and v il(dc) to the ball being tested, and then measuring current, i(v ih[ac] ), and i(v il[ac] ), respectively. 2. minimum it and at device values are derated by six percent when the devices operate between C40c and 0c (t c ). 3. measure voltage (vm) at tested ball with no load. 512mb: x4, x8, x16 ddr2 sdram odt dc electrical characteristics pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 43 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. input electrical characteristics and operating conditions table 15: input dc logic levels all voltages are referenced to v ss parameter symbol min max units input high (logic 1) voltage v ih(dc) v ref(dc) + 125 v ddq 1 mv input low (logic 0) voltage v il(dc) C300 v ref(dc) - 125 mv note: 1. v ddq + 300mv allowed provided 1.9v is not exceeded. table 16: input ac logic levels all voltages are referenced to v ss parameter symbol min max units input high (logic 1) voltage (-37e/-5e) v ih(ac) v ref(dc) + 250 v ddq 1 mv input high (logic 1) voltage (-187e/-25e/-25/-3e/-3) v ih(ac) v ref(dc) + 200 v ddq 1 mv input low (logic 0) voltage (-37e/-5e) v il(ac) C300 v ref(dc) - 250 mv input low (logic 0) voltage (-187e/-25e/-25/-3e/-3) v il(ac) C300 v ref(dc) - 200 mv note: 1. refer to ac overshoot/undershoot specification (page 54). figure 11: single-ended input signal levels 650mv 775mv 864mv 882mv 900mv 918mv 936mv 1,025mv 1,150mv v il(ac) v il(dc) v ref - ac noise v ref - dc error v ref + dc error v ref + ac noise v ih(dc) v ih(ac) note: 1. numbers in diagram reflect nominal ddr2-400/ddr2-533 values. 512mb: x4, x8, x16 ddr2 sdram input electrical characteristics and operating conditions pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 44 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 17: differential input logic levels all voltages referenced to v ss parameter symbol min max units notes dc input signal voltage v in(dc) C300 v ddq mv 1, 6 dc differential input voltage v id(dc) 250 v ddq mv 2, 6 ac differential input voltage v id(ac) 500 v ddq mv 3, 6 ac differential cross-point voltage v ix(ac) 0.50 v ddq - 175 0.50 v ddq + 175 mv 4 input midpoint voltage v mp(dc) 850 950 mv 5 notes: 1. v in(dc) specifies the allowable dc execution of each input of differential pair such as ck, ck#, dqs, dqs#, ldqs, ldqs#, udqs, udqs#, and rdqs, rdqs#. 2. v id(dc) specifies the input differential voltage |v tr - v cp | required for switching, where v tr is the true input (such as ck, dqs, ldqs, udqs) level and v cp is the complementary input (such as ck#, dqs#, ldqs#, udqs#) level. the minimum value is equal to v ih(dc) - v il(dc) . differential input signal levels are shown in figure 12. 3. v id(ac) specifies the input differential voltage |v tr - v cp | required for switching, where v tr is the true input (such as ck, dqs, ldqs, udqs, rdqs) level and v cp is the comple- mentary input (such as ck#, dqs#, ldqs#, udqs#, rdqs#) level. the minimum value is equal to v ih(ac) - v il(ac) , as shown in table 16 (page 44). 4. the typical value of v ix(ac) is expected to be about 0.5 v ddq of the transmitting device and v ix(ac) is expected to track variations in v ddq . v ix(ac) indicates the voltage at which differential input signals must cross, as shown in figure 12. 5. v mp(dc) specifies the input differential common mode voltage (v tr + v cp )/2 where v tr is the true input (ck, dqs) level and v cp is the complementary input (ck#, dqs#). v mp(dc) is expected to be approximately 0.5 v ddq . 6. v ddq + 300mv allowed provided 1.9v is not exceeded. figure 12: differential input signal levels tr 2 cp 2 2.1v v ddq = 1.8v v in(dc)max 1 v in(dc)min 1 C0.30v 0.9v 1.075v 0.725v v id(ac) 6 v id(dc) 5 x v mp(dc) 3 v ix(ac) 4 x notes: 1. tr and cp may not be more positive than v ddq + 0.3v or more negative than v ss - 0.3v. 2. tr represents the ck, dqs, rdqs, ldqs, and udqs signals; cp represents ck#, dqs#, rdqs#, ldqs#, and udqs# signals. 3. this provides a minimum of 850mv to a maximum of 950mv and is expected to be v ddq /2. 4. tr and cp must cross in this region. 5. tr and cp must meet at least v id(dc)min when static and is centered around v mp(dc) . 6. tr and cp must have a minimum 500mv peak-to-peak swing. 512mb: x4, x8, x16 ddr2 sdram input electrical characteristics and operating conditions pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 45 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. 7. numbers in diagram reflect nominal values (v ddq = 1.8v). 512mb: x4, x8, x16 ddr2 sdram input electrical characteristics and operating conditions pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 46 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. output electrical characteristics and operating conditions table 18: differential ac output parameters parameter symbol min max units notes ac differential cross-point voltage v ox(ac) 0.50 v ddq - 125 0.50 v ddq + 125 mv 1 ac differential voltage swing vswing 1.0 C mv note: 1. the typical value of v ox(ac) is expected to be about 0.5 v ddq of the transmitting de- vice and v ox(ac) is expected to track variations in v ddq . v ox(ac) indicates the voltage at which differential output signals must cross. figure 13: differential output signal levels crossing point v ox v ssq vswing v ddq v tr v cp table 19: output dc current drive parameter symbol value units notes output min source dc current i oh C13.4 ma 1, 2, 4 output min sink dc current i ol 13.4 ma 2, 3, 4 notes: 1. for i oh(dc) ; v ddq = 1.7v, v out = 1,420mv. (v out - v ddq )/i oh must be less than 21 for values of v out between v ddq and v ddq - 280mv. 2. for i ol(dc) ; v ddq = 1.7v, v out = 280mv. v out /i ol must be less than 21 for values of v out between 0v and 280mv. 3. the dc value of v ref applied to the receiving device is set to v tt . 4. the values of i oh(dc) and i ol(dc) are based on the conditions given in notes 1 and 2. they are used to test device drive current capability to ensure v ih,min plus a noise margin and v il,max minus a noise margin are delivered to an sstl_18 receiver. the actual current val- ues are derived by shifting the desired driver operating point (see output iv curves) along a 21 load line to define a convenient driver current for measurement. 512mb: x4, x8, x16 ddr2 sdram output electrical characteristics and operating conditions pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 47 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 20: output characteristics parameter min nom max units notes output impedance see output driver characteristics (page 49) 1, 2 pull-up and pull-down mismatch 0 C 4 1, 2, 3 output slew rate 1.5 C 5 v/ns 1, 4, 5, 6 notes: 1. absolute specifications: 0c t c +85c; v ddq = +1.8v 0.1v, v dd = +1.8v 0.1v. 2. impedance measurement conditions for output source dc current: v ddq = 1.7v; v out = 1420mv; (v out - v ddq )/i oh must be less than 23.4 for values of v out between v ddq and v ddq - 280mv. the impedance measurement condition for output sink dc cur- rent: v ddq = 1.7v; v out = 280mv; v out /i ol must be less than 23.4 for values of v out between 0v and 280mv. 3. mismatch is an absolute value between pull-up and pull-down; both are measured at the same temperature and voltage. 4. output slew rate for falling and rising edges is measured between v tt - 250mv and v tt + 250mv for single-ended signals. for differential signals (dqs, dqs#), output slew rate is measured between dqs - dqs# = C500mv and dqs# - dqs = +500mv. output slew rate is guaranteed by design but is not necessarily tested on each device. 5. the absolute value of the slew rate as measured from v il(dc)max to v ih(dc)min is equal to or greater than the slew rate as measured from v il(ac)max to v ih(ac)min . this is guaran- teed by design and characterization. 6. it and at devices require an additional 0.4 v/ns in the max limit when t c is between C 40c and 0c. figure 14: output slew rate load output (v out ) reference point 25 v tt = v ddq /2 512mb: x4, x8, x16 ddr2 sdram output electrical characteristics and operating conditions pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 48 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. output driver characteristics figure 15: full strength pull-down characteristics v out (v) 0.0 0.5 1.0 1.5 120 100 80 60 40 20 0 i out (ma) table 21: full strength pull-down current (ma) voltage (v) min nom max 0.0 0.00 0.00 0.00 0.1 4.30 5.63 7.95 0.2 8.60 11.30 15.90 0.3 12.90 16.52 23.85 0.4 16.90 22.19 31.80 0.5 20.40 27.59 39.75 0.6 23.28 32.39 47.70 0.7 25.44 36.45 55.55 0.8 26.79 40.38 62.95 0.9 27.67 44.01 69.55 1.0 28.38 47.01 75.35 1.1 28.96 49.63 80.35 1.2 29.46 51.71 84.55 1.3 29.90 53.32 87.95 1.4 30.29 54.9 90.70 1.5 30.65 56.03 93.00 1.6 30.98 57.07 95.05 1.7 31.31 58.16 97.05 1.8 31.64 59.27 99.05 1.9 31.96 60.35 101.05 512mb: x4, x8, x16 ddr2 sdram output driver characteristics pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 49 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 16: full strength pull-up characteristics v ddq - v out (v) 0 C20 C40 C60 C80 C100 C120 0 0.5 1.0 1.5 i out (ma) table 22: full strength pull-up current (ma) voltage (v) min nom max 0.0 0.00 0.00 0.00 0.1 C4.30 C5.63 C7.95 0.2 C8.60 C11.30 C15.90 0.3 C12.90 C16.52 C23.85 0.4 C16.90 C22.19 C31.80 0.5 C20.40 C27.59 C39.75 0.6 C23.28 C32.39 C47.70 0.7 C25.44 C36.45 C55.55 0.8 C26.79 C40.38 C62.95 0.9 C27.67 C44.01 C69.55 1.0 C28.38 C47.01 C75.35 1.1 C28.96 C49.63 C80.35 1.2 C29.46 C51.71 C84.55 1.3 C29.90 C53.32 C87.95 1.4 C30.29 C54.90 C90.70 1.5 C30.65 C56.03 C93.00 1.6 C30.98 C57.07 C95.05 1.7 C31.31 C58.16 C97.05 1.8 C31.64 C59.27 C99.05 1.9 C31.96 C60.35 C101.05 512mb: x4, x8, x16 ddr2 sdram output driver characteristics pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 50 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 17: reduced strength pull-down characteristics 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 v out (v) i out (mv) table 23: reduced strength pull-down current (ma) voltage (v) min nom max 0.0 0.00 0.00 0.00 0.1 1.72 2.98 4.77 0.2 3.44 5.99 9.54 0.3 5.16 8.75 14.31 0.4 6.76 11.76 19.08 0.5 8.16 14.62 23.85 0.6 9.31 17.17 28.62 0.7 10.18 19.32 33.33 0.8 10.72 21.40 37.77 0.9 11.07 23.32 41.73 1.0 11.35 24.92 45.21 1.1 11.58 26.30 48.21 1.2 11.78 27.41 50.73 1.3 11.96 28.26 52.77 1.4 12.12 29.10 54.42 1.5 12.26 29.70 55.80 1.6 12.39 30.25 57.03 1.7 12.52 30.82 58.23 1.8 12.66 31.41 59.43 1.9 12.78 31.98 60.63 512mb: x4, x8, x16 ddr2 sdram output driver characteristics pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 51 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 18: reduced strength pull-up characteristics 0 C10 C20 C30 C40 C50 C60 C70 0.0 0.5 1.0 1.5 v ddq - v out (v) i out (mv) table 24: reduced strength pull-up current (ma) voltage (v) min nom max 0.0 0.00 0.00 0.00 0.1 C1.72 C2.98 C4.77 0.2 C3.44 C5.99 C9.54 0.3 C5.16 C8.75 C14.31 0.4 C6.76 C11.76 C19.08 0.5 C8.16 C14.62 C23.85 0.6 C9.31 C17.17 C28.62 0.7 C10.18 C19.32 C33.33 0.8 C10.72 C21.40 C37.77 0.9 C11.07 C23.32 C41.73 1.0 C11.35 C24.92 C45.21 1.1 C11.58 C26.30 C48.21 1.2 C11.78 C27.41 C50.73 1.3 C11.96 C28.26 C52.77 1.4 C12.12 C29.10 C54.42 1.5 C12.26 C29.69 C55.8 1.6 C12.39 C30.25 C57.03 1.7 C12.52 C30.82 C58.23 1.8 C12.66 C31.42 C59.43 1.9 C12.78 C31.98 C60.63 512mb: x4, x8, x16 ddr2 sdram output driver characteristics pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 52 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. power and ground clamp characteristics power and ground clamps are provided on the following input-only balls: address balls, bank address balls, cs#, ras#, cas#, we#, odt, and cke. table 25: input clamp characteristics voltage across clamp (v) minimum power clamp current (ma) minimum ground clamp current (ma) 0.0 0.0 0.0 0.1 0.0 0.0 0.2 0.0 0.0 0.3 0.0 0.0 0.4 0.0 0.0 0.5 0.0 0.0 0.6 0.0 0.0 0.7 0.0 0.0 0.8 0.1 0.1 0.9 1.0 1.0 1.0 2.5 2.5 1.1 4.7 4.7 1.2 6.8 6.8 1.3 9.1 9.1 1.4 11.0 11.0 1.5 13.5 13.5 1.6 16.0 16.0 1.7 18.2 18.2 1.8 21.0 21.0 figure 19: input clamp characteristics voltage across clamp (v) minimum clamp current (ma) 25 20 15 10 5 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 512mb: x4, x8, x16 ddr2 sdram power and ground clamp characteristics pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 53 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. ac overshoot/undershoot specification some revisions will support the 0.9v maximum average amplitude instead of the 0.5v maximum average amplitude shown in table 26 and table 27. table 26: address and control balls applies to address balls, bank address balls, cs#, ras#, cas#, we#, cke, and odt parameter specification -187e -25/-25e -3/-3e -37e -5e maximum peak amplitude allowed for overshoot area (see figure 20) 0.50v 0.50v 0.50v 0.50v 0.50v maximum peak amplitude allowed for undershoot area (see figure 21) 0.50v 0.50v 0.50v 0.50v 0.50v maximum overshoot area above v dd (see figure 20) 0.5 vns 0.66 vns 0.80 vns 1.00 vns 1.33 vns maximum undershoot area below v ss (see figure 21) 0.5 vns 0.66 vns 0.80 vns 1.00 vns 1.33 vns table 27: clock, data, strobe, and mask balls applies to dq, dqs, dqs#, rdqs, rdqs#, udqs, udqs#, ldqs, ldqs#, dm, udm, and ldm parameter specification -187e -25/-25e -3/-3e -37e -5e maximum peak amplitude allowed for overshoot area (see figure 20) 0.50v 0.50v 0.50v 0.50v 0.50v maximum peak amplitude allowed for undershoot area (see figure 21) 0.50v 0.50v 0.50v 0.50v 0.50v maximum overshoot area above v ddq (see figure 20) 0.19 vns 0.23 vns 0.23 vns 0.28 vns 0.38 vns maximum undershoot area below v ssq (see figure 21) 0.19 vns 0.23 vns 0.23 vns 0.28 vns 0.38 vns figure 20: overshoot maximum amplitude overshoot area v dd /v ddq v ss /v ssq volts (v) time (ns) figure 21: undershoot v ss /v ssq maximum amplitude undershoot area time (ns) volts (v) 512mb: x4, x8, x16 ddr2 sdram ac overshoot/undershoot specification pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 54 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 28: ac input test conditions parameter symbol min max units notes input setup timing measurement reference level address balls, bank address balls, cs#, ras#, cas#, we#, odt, dm, udm, ldm, and cke v rs see note 2 1, 2, 3, 4 input hold timing measurement reference level address balls, bank address balls, cs#, ras#, cas#, we#, odt, dm, udm, ldm, and cke v rh see note 5 1, 3, 4, 5 input timing measurement reference level (single-ended) dqs for x4, x8; udqs, ldqs for x16 v ref(dc) v ddq 0.49 v ddq 0.51 v 1, 3, 4, 6 input timing measurement reference level (differential) ck, ck# for x4, x8, x16; dqs, dqs# for x4, x8; rdqs, rdqs# for x8; udqs, udqs#, ldqs, ldqs# for x16 v rd v ix(ac) v 1, 3, 7, 8, 9 notes: 1. all voltages referenced to v ss . 2. input waveform setup timing ( t is b ) is referenced from the input signal crossing at the v ih(ac) level for a rising signal and v il(ac) for a falling signal applied to the device under test, as shown in figure 30 (page 67). 3. see input slew rate derating (page 56). 4. the slew rate for single-ended inputs is measured from dc level to ac level, v il(dc) to v ih(ac) on the rising edge and v il(ac) to v ih(dc) on the falling edge. for signals referenced to v ref , the valid intersection is where the tangent line intersects v ref , as shown in figure 23 (page 59), figure 25 (page 60), figure 27 (page 65), and figure 29 (page 66). 5. input waveform hold ( t ih b ) timing is referenced from the input signal crossing at the v il(dc) level for a rising signal and v ih(dc) for a falling signal applied to the device under test, as shown in figure 30 (page 67). 6. input waveform setup timing ( t ds) and hold timing ( t dh) for single-ended data strobe is referenced from the crossing of dqs, udqs, or ldqs through the vref level applied to the device under test, as shown in figure 32 (page 68). 7. input waveform setup timing ( t ds) and hold timing ( t dh) when differential data strobe is enabled is referenced from the cross-point of dqs/dqs#, udqs/udqs#, or ldqs/ ldqs#, as shown in figure 31 (page 67). 8. input waveform timing is referenced to the crossing point level (v ix ) of two input signals (v tr and v cp ) applied to the device under test, where v tr is the true input signal and v cp is the complementary input signal, as shown in figure 33 (page 68). 9. the slew rate for differentially ended inputs is measured from twice the dc level to twice the ac level: 2 v il(dc) to 2 v ih(ac) on the rising edge and 2 v il(ac) to 2 v ih(dc) on the falling edge. for example, the ck/ck# would be C250mv to +500mv for ck rising edge and would be +250mv to C500mv for ck falling edge. 512mb: x4, x8, x16 ddr2 sdram ac overshoot/undershoot specification pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 55 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. input slew rate derating for all input signals, the total t is (setup time) and t ih (hold time) required is calculated by adding the data sheet t is (base) and t ih (base) value to the t is and t ih derating value, respectively. example: t is (total setup time) = t is (base) + t is. t is, the nominal slew rate for a rising signal, is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac)min . setup nominal slew rate ( t is) for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v il(ac)max . if the actual signal is always earlier than the nominal slew rate line between shaded v ref(dc) to ac region, use the nominal slew rate for the derating value (figure 22 (page 59)). if the actual signal is later than the nominal slew rate line anywhere between the sha- ded v ref(dc) to ac region, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for the derating value (see figure 23 (page 59)). t ih, the nominal slew rate for a rising signal, is defined as the slew rate between the last crossing of v il(dc)max and the first crossing of v ref(dc) . t ih, nominal slew rate for a fall- ing signal, is defined as the slew rate between the last crossing of v ih(dc)min and the first crossing of v ref(dc) . if the actual signal is always later than the nominal slew rate line between shaded dc to v ref(dc) region, use the nominal slew rate for the derating value (figure 24 (page 60)). if the actual signal is earlier than the nominal slew rate line anywhere between shaded dc to v ref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to v ref(dc) level is used for the derating value (figure 25 (page 60)). although the total setup time might be negative for slow slew rates (a valid input signal will not have reached v ih[ac] /v il[ac] at the time of the rising clock transition), a valid input signal is still required to complete the transition and reach v ih(ac) /v il(ac) . for slew rates in between the values listed in table 29 (page 57) and table 30 (page 58), the derating values may obtained by linear interpolation. 512mb: x4, x8, x16 ddr2 sdram input slew rate derating pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 56 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 29: ddr2-400/533 setup and hold time derating values ( t is and t ih) command/address slew rate (v/ns) ck, ck# differential slew rate units 2.0 v/ns 1.5 v/ns 1.0 v/ns t is t ih t is t ih t is t ih 4.0 +187 +94 +217 +124 +247 +154 ps 3.5 +179 +89 +209 +119 +239 +149 ps 3.0 +167 +83 +197 +113 +227 +143 ps 2.5 +150 +75 +180 +105 +210 +135 ps 2.0 +125 +45 +155 +75 +185 +105 ps 1.5 +83 +21 +113 +51 +143 +81 ps 1.0 0 0 +30 +30 +60 +60 ps 0.9 C11 C14 +19 +16 +49 +46 ps 0.8 C25 C31 +5 C1 +35 +29 ps 0.7 C43 C54 C13 C24 +17 +6 ps 0.6 C67 C83 C37 C53 C7 C23 ps 0.5 C110 C125 C80 C95 C50 C65 ps 0.4 C175 C188 C145 C158 C115 C128 ps 0.3 C285 C292 C255 C262 C225 C232 ps 0.25 C350 C375 C320 C345 C290 C315 ps 0.2 C525 C500 C495 C470 C465 C440 ps 0.15 C800 C708 C770 C678 C740 C648 ps 0.1 C1,450 C1,125 C1,420 C1,095 C1,390 C1,065 ps 512mb: x4, x8, x16 ddr2 sdram input slew rate derating pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 57 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 30: ddr2-667/800/1066 setup and hold time derating values ( t is and t ih) command/ address slew rate (v/ns) ck, ck# differential slew rate units 2.0 v/ns 1.5 v/ns 1.0 v/ns t is t ih t is t ih t is t ih 4.0 +150 +94 +180 +124 +210 +154 ps 3.5 +143 +89 +173 +119 +203 +149 ps 3.0 +133 +83 +163 +113 +193 +143 ps 2.5 +120 +75 +150 +105 +180 +135 ps 2.0 +100 +45 +160 +75 +160 +105 ps 1.5 +67 +21 +97 +51 +127 +81 ps 1.0 0 0 +30 +30 +60 +60 ps 0.9 C5 C14 +25 +16 +55 +46 ps 0.8 C13 C31 +17 C1 +47 +29 ps 0.7 C22 C54 +8 C24 +38 +6 ps 0.6 C34 C83 C4 C53 +36 C23 ps 0.5 C60 C125 C30 C95 0 C65 ps 0.4 C100 C188 C70 C158 C40 C128 ps 0.3 C168 C292 C138 C262 C108 C232 ps 0.25 C200 C375 C170 C345 C140 C315 ps 0.2 C325 C500 C295 C470 C265 C440 ps 0.15 C517 C708 C487 C678 C457 C648 ps 0.1 C1,000 C1,125 C970 C1,095 C940 C1,065 ps 512mb: x4, x8, x16 ddr2 sdram input slew rate derating pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 58 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 22: nominal slew rate for t is v ss ck# ck t ih t is t ih setup slew rate rising signal setup slew rate falling signal tf tr t f = v ih(ac)min - v ref (dc) t r = v ddq t is nominal slew rate v ref to ac region v ref to ac region v ref (dc) - v il (ac)max v ih(dc)min v ref(dc) v il(ac)max v il(dc)max v ih(ac)min nominal slew rate figure 23: tangent line for t is setup slew rate rising signal tf tr t an g ent li n e ( v ih[ac]min - v ref[dc] ) tr = tangent line tangent line v ref to ac region nominal line t ih t is t ih t is v ss ck# ck v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)max v il(ac)max v ref to ac region nominal line 512mb: x4, x8, x16 ddr2 sdram input slew rate derating pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 59 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 24: nominal slew rate for t ih tr tf nominal slew rate dc to v ref region t ih t is t is v ss ck# ck v ddq v ih(dc)min v ref(dc) v il(ac)max v il(dc)max v ih(ac)min dc to v ref region nominal slew rate t ih figure 25: tangent line for t ih tangent line dc to v ref region t ih t is t is v ss v ddq v ih(dc)min v ref(dc) v il(ac)max v il(dc)max v ih(ac)min dc to v ref region tangent line t ih ck ck# hold slew rate falling signal tf tr t a n ge n t l i ne ( v ih [dc ]min - v ref[dc] ) t f = nominal line hold slew rate rising signal t an g ent lin e (v ref[dc] - v il [dc ]max ) tr = nominal line 512mb: x4, x8, x16 ddr2 sdram input slew rate derating pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 60 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 31: ddr2-400/533 t ds, t dh derating values with differential strobe all units are shown in picoseconds dq slew rate (v/ns) dqs, dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 125 45 125 45 125 45 C C C C C C C C C C C C 1.5 83 21 83 21 83 21 95 33 C C C C C C C C C C 1.0 0 0 0 0 0 0 12 12 24 24 C C C C C C C C 0.9 C C C11 C14 C11 C14 1 C2 13 10 25 22 C C C C C C 0.8 C C C C C25 C31 C13 C19 C1 C7 11 5 23 17 C C C C 0.7 C C C C C C C31 C42 C19 C30 C7 C18 5 C6 17 6 C C 0.6 C C C C C C C C C43 C59 C31 C47 C19 C35 C7 C23 5 C11 0.5 C C C C C C C C C C C74 C89 C62 C77 C50 C65 C38 C53 0.4 C C C C C C C C C C C C C127 C140 C115 C128 C103 C116 notes: 1. for all input signals, the total t ds and t dh required is calculated by adding the data sheet value to the derating value listed in table 31. 2. t ds nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac)min . t ds nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first cross- ing of v il(ac)max . if the actual signal is always earlier than the nominal slew rate line between the shaded v ref(dc) to ac region, use the nominal slew rate for the derating value (see figure 26 (page 65)). if the actual signal is later than the nominal slew rate line anywhere between the shaded v ref(dc) to ac region, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for the derating value (see figure 27 (page 65)). 3. t dh nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il(dc)max and the first crossing of v ref(dc) . t dh nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih(dc)min and the first cross- ing of v ref(dc) . if the actual signal is always later than the nominal slew rate line between the shaded dc level to v ref(dc) region, use the nominal slew rate for the de- rating value (see figure 28 (page 66)). if the actual signal is earlier than the nominal slew rate line anywhere between shaded dc to v ref(dc) region, the slew rate of a tan- gent line to the actual signal from the dc level to v ref(dc) level is used for the derating value (see figure 29 (page 66)). 4. although the total setup time might be negative for slow slew rates (a valid input signal will not have reached v ih[ac] /v il[ac] at the time of the rising clock transition), a valid in- put signal is still required to complete the transition and reach v ih(ac) /v il(ac) . 5. for slew rates between the values listed in this table, the derating values may be ob- tained by linear interpolation. 6. these values are typically not subject to production test. they are verified by design and characterization. 7. single-ended dqs requires special derating. the values in table 33 (page 63) are the dqs single-ended slew rate derating with dqs referenced at v ref and dq referenced at the logic levels t ds b and t dh b . converting the derated base values from dq referenced to the ac/dc trip points to dq referenced to v ref is listed in table 35 (page 64) and table 36 (page 64). table 35 provides the v ref -based fully derated values for the dq ( t ds a and t dh a ) for ddr2-533. table 36 provides the v ref -based fully derated values for the dq ( t ds a and t dh a ) for ddr2-400. 512mb: x4, x8, x16 ddr2 sdram input slew rate derating pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 61 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 32: ddr2-667/800/1066 t ds, t dh derating values with differential strobe all units are shown in picoseconds dq slew rate (v/ns) dqs, dqs# differential slew rate 2.8 v/ns 2.4 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 100 63 100 63 100 63 112 75 124 87 136 99 148 111 160 123 172 135 1.5 67 42 67 42 67 42 79 54 91 66 103 78 115 90 127 102 139 114 1.0 0 0 0 0 0 0 12 12 24 24 36 36 48 48 60 60 72 72 0.9 C5 C14 C5 C14 C5 C14 7 C2 19 10 31 22 43 34 55 46 67 58 0.8 C13 C31 C13 C31 C13 C31 C1 C19 11 C7 23 5 35 17 47 29 59 41 0.7 C22 C54 C22 C54 C22 C54 C10 C42 2 C30 14 C18 26 C6 38 6 50 18 0.6 C34 C83 C34 C83 C34 C83 C22 C71 C10 C59 2 C47 14 C35 26 C23 38 C11 0.5 C60 C125 C60 C125 C60 C125 C48 C113 C36 C101 C24 C89 C12 C77 0 C65 12 C53 0.4 C100 C188 C100 C188 C100 C188 C88 C176 C76 C164 C64 C152 C52 C140 C40 C128 C28 C116 notes: 1. for all input signals the total t ds and t dh required is calculated by adding the data sheet value to the derating value listed in table 32. 2. t ds nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac)min . t ds nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first cross- ing of v il(ac)max . if the actual signal is always earlier than the nominal slew rate line between the shaded v ref(dc) to ac region, use the nominal slew rate for the derating value (see figure 26 (page 65)). if the actual signal is later than the nominal slew rate line anywhere between shaded v ref(dc) to ac region, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for the derating value (see fig- ure 27 (page 65)). 3. t dh nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il(dc)max and the first crossing of v ref(dc) . t dh nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih(dc)min and the first cross- ing of v ref(dc) . if the actual signal is always later than the nominal slew rate line between the shaded dc level to v ref(dc) region, use the nominal slew rate for the de- rating value (see figure 28 (page 66)). if the actual signal is earlier than the nominal slew rate line anywhere between the shaded dc to v ref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to v ref(dc) level is used for the derat- ing value (see figure 29 (page 66)). 4. although the total setup time might be negative for slow slew rates (a valid input signal will not have reached v ih[ac] /v il[ac] at the time of the rising clock transition), a valid in- put signal is still required to complete the transition and reach v ih(ac) /v il(ac) . 5. for slew rates between the values listed in this table, the derating values may be ob- tained by linear interpolation. 6. these values are typically not subject to production test. they are verified by design and characterization. 7. single-ended dqs requires special derating. the values in table 33 (page 63) are the dqs single-ended slew rate derating with dqs referenced at v ref and dq referenced at the logic levels t ds b and t dh b . converting the derated base values from dq referenced to the ac/dc trip points to dq referenced to v ref is listed in table 34 (page 63). ta- ble 34 provides the v ref -based fully derated values for the dq ( t ds a and t dh a ) for 512mb: x4, x8, x16 ddr2 sdram input slew rate derating pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 62 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. ddr2-667. it is not advised to operate ddr2-800 and ddr2-1066 devices with single- ended dqs; however, table 33 would be used with the base values. table 33: single-ended dqs slew rate derating values using t ds b and t dh b reference points indicated in bold; derating values are to be used with base t ds b - and t dh b- -specified values dq (v/ns) dqs single-ended slew rate derated (at v ref ) 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns 0.6 v/ns 0.4 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 130 53 130 53 130 53 130 53 130 53 145 48 155 45 165 41 175 38 1.5 97 32 97 32 97 32 97 32 97 32 112 27 122 24 132 20 142 17 1.0 30 C10 30 C10 30 C10 30 C10 30 C10 45 C15 55 C18 65 C22 75 C25 0.9 25 C24 25 C24 25 C24 25 C24 25 C24 40 C29 50 C32 60 C36 70 C39 0.8 17 C41 17 C41 17 C41 17 C41 17 C41 32 C46 42 C49 52 C53 61 C56 0.7 5 C64 5 C64 5 C64 5 C64 5 C64 20 C69 30 C72 40 C75 50 C79 0.6 C7 C93 C7 C93 C7 C93 C7 C93 C7 C93 8 C98 18 C102 28 C105 38 C108 0.5 C28 C135 C28 C135 C28 C135 C28 C135 C28 C135 C13 C140 C3 C143 7 C147 17 C150 0.4 C78 C198 C78 C198 C78 C198 C78 C198 C78 C198 C63 C203 C53 C206 C43 C210 C33 C213 table 34: single-ended dqs slew rate fully derated (dqs, dq at v ref ) at ddr2-667 reference points indicated in bold dq (v/ns) dqs single-ended slew rate derated (at v ref ) 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns 0.6 v/ns 0.4 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 330 291 330 291 330 291 330 291 330 291 345 286 355 282 365 29 375 276 1.5 330 290 330 290 330 290 330 290 330 290 345 285 355 282 365 279 375 275 1.0 330 290 330 290 330 290 330 290 330 290 345 285 355 282 365 278 375 275 0.9 347 290 347 290 347 290 347 290 347 290 362 285 372 282 382 278 392 275 0.8 367 290 367 290 367 290 367 290 367 290 382 285 392 282 402 278 412 275 0.7 391 290 391 290 391 290 391 290 391 290 406 285 416 281 426 278 436 275 0.6 426 290 426 290 426 290 426 290 426 290 441 285 451 282 461 278 471 275 0.5 472 290 472 290 472 290 472 290 472 290 487 285 497 282 507 278 517 275 0.4 522 289 522 289 522 289 522 289 522 289 537 284 547 281 557 278 567 274 512mb: x4, x8, x16 ddr2 sdram input slew rate derating pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 63 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 35: single-ended dqs slew rate fully derated (dqs, dq at v ref ) at ddr2-533 reference points indicated in bold dq (v/ns) dqs single-ended slew rate derated (at v ref ) 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns 0.6 v/ns 0.4 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 355 341 355 341 355 341 355 341 355 341 370 336 380 332 390 329 400 326 1.5 364 340 364 340 364 340 364 340 364 340 379 335 389 332 399 329 409 325 1.0 380 340 380 340 380 340 380 340 380 340 395 335 405 332 415 328 425 325 0.9 402 340 402 340 402 340 402 340 402 340 417 335 427 332 437 328 447 325 0.8 429 340 429 340 429 340 429 340 429 340 444 335 454 332 464 328 474 325 0.7 463 340 463 340 463 340 463 340 463 340 478 335 488 331 498 328 508 325 0.6 510 340 510 340 510 340 510 340 510 340 525 335 535 332 545 328 555 325 0.5 572 340 572 340 572 340 572 340 572 340 587 335 597 332 607 328 617 325 0.4 647 339 647 339 647 339 647 339 647 339 662 334 672 331 682 328 692 324 table 36: single-ended dqs slew rate fully derated (dqs, dq at v ref ) at ddr2-400 reference points indicated in bold dq (v/ns) dqs single-ended slew rate derated (at v ref ) 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns 0.6 v/ns 0.4 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 405 391 405 391 405 391 405 391 405 391 420 386 430 382 440 379 450 376 1.5 414 390 414 390 414 390 414 390 414 390 429 385 439 382 449 379 459 375 1.0 430 390 430 390 430 390 430 390 430 390 445 385 455 382 465 378 475 375 0.9 452 390 452 390 452 390 452 390 452 390 467 385 477 382 487 378 497 375 0.8 479 390 479 390 479 390 479 390 479 390 494 385 504 382 514 378 524 375 0.7 513 390 513 390 513 390 513 390 513 390 528 385 538 381 548 378 558 375 0.6 560 390 560 390 560 390 560 390 560 390 575 385 585 382 595 378 605 375 0.5 622 390 622 390 622 390 622 390 622 390 637 385 647 382 657 378 667 375 0.4 697 389 697 389 697 389 697 389 697 389 712 384 722 381 732 378 742 374 512mb: x4, x8, x16 ddr2 sdram input slew rate derating pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 64 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 26: nominal slew rate for t ds v ref to ac region v ref to ac region setup slew rate rising signal setup slew rate falling signal t f tr v ref(dc) - v il(ac)max tf = v ih(ac)min - v ref(dc) tr = nominal slew rate v ss dqs# 1 dqs 1 v ddq v ih(dc)min v ref(dc) v il(ac)max v il(dc)max v ih(ac)min t dh t ds nominal slew rate t dh t ds note: 1. dqs, dqs# signals must be monotonic between v il(dc)max and v ih(dc)min . figure 27: tangent line for t ds t f tr setup slew rate rising signal setup slew rate falling signal tangent line (v ref[dc] - v il[ac]max ) tf = tangent line (v ih[ac]min - v ref[dc] ) tr = t dh t ds t dh t ds v ss dqs# 1 dqs 1 v ddq v ih(dc)min v ref(dc) v il(ac)max v il(dc)max v ih(ac)min nominal line tangent line nominal line tangent line v ref to ac region v ref to ac region note: 1. dqs, dqs# signals must be monotonic between v il(dc)max and v ih(dc)min . 512mb: x4, x8, x16 ddr2 sdram input slew rate derating pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 65 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 28: nominal slew rate for t dh hold slew rate falling signal hold slew rate rising signal v ref(dc) - v il(dc)max t r = v ih(dc)min - v ref(dc) tf = tr tf nominal slew rate dc to v ref region t ih t is t is v ss dqs# 1 dqs 1 v ddq v ih(dc)min v ref(dc) v il(ac)max v il(dc)max v ih(ac)min dc to v ref region nominal slew rate t ih note: 1. dqs, dqs# signals must be monotonic between v il(dc)max and v ih(dc)min . figure 29: tangent line for t dh tangent line dc to v ref region t ih t is t is v ss v ddq v ih(dc)min v ref(dc) v il(ac)max v il(dc)max v ih(ac)min dc to v ref region tangent line t ih dqs 1 dqs# 1 hold slew rate falling signal tf tr t a n ge n t l i ne ( v ih [dc ]min - v ref[dc] ) tf = nominal line hold slew rate rising signal t an g ent lin e (v ref[dc] - v il [dc ]max ) tr = nominal line note: 1. dqs, dqs# signals must be monotonic between v il(dc)max and v ih(dc)min . 512mb: x4, x8, x16 ddr2 sdram input slew rate derating pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 66 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 30: ac input test signal waveform command/address balls t is a logic levels v ref levels t ih a t is a t ih a t is b t ih b t is b t ih b ck# ck v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)min v il(ac)min v ssq vswing (max) figure 31: ac input test signal waveform for data with dqs, dqs# (differential) dqs# dqs t ds a t dh a t ds a t dh a t ds b t dh b t ds b t dh b logic levels v ref levels v ref(dc) vil(dc)max vil(ac)max v ssq v ih(dc)min v ih(ac)min v ddq vswing (max) 512mb: x4, x8, x16 ddr2 sdram input slew rate derating pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 67 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 32: ac input test signal waveform for data with dqs (single-ended) dqs v ref v ref(dc) v il(dc)max v il(ac)max v ssq v ih(dc)min v ih(ac)min v ddq vswing (max) logic levels v ref levels t ds a t dh a t ds a t dh a t ds b t dh b t ds b t dh b figure 33: ac input test signal waveform (differential) v tr vswing v cp v ddq v ssq v ix crossing point 512mb: x4, x8, x16 ddr2 sdram input slew rate derating pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 68 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. commands truth tables the following tables provide a quick reference of available ddr2 sdram commands, including cke power-down modes and bank-to-bank commands. table 37: truth table C ddr2 commands notes: 1C3 apply to the entire table function cke cs# ras# cas# we# ba2C ba0 a n Ca11 a10 a9Ca0 notes previous cycle current cycle load mode h h l l l l ba op code 4, 6 refresh h h l l l h x x x x self refresh entry h l l l l h x x x x self refresh exit l h h x x x x x x x 4, 7 l h h h single bank precharge h h l l h l ba x l x 6 all banks precharge h h l l h l x x h x bank activate h h l l h h ba row address 4 write h h l h l l ba column address l column address 4, 5, 6, 8 write with auto precharge h h l h l l ba column address h column address 4, 5, 6, 8 read h h l h l h ba column address l column address 4, 5, 6, 8 read with auto precharge h h l h l h ba column address h column address 4, 5, 6, 8 no operation h x l h h h x x x x device deselect h x h x x x x x x x power-down entry h l h x x x x x x x 9 l h h h power-down exit l h h x x x x x x x 9 l h h h notes: 1. all ddr2 sdram commands are defined by states of cs#, ras#, cas#, we#, and cke at the rising edge of the clock. 2. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. see odt timing (page 126) for details. 3. x means h or l (but a defined logic level) for valid i dd measurements. 4. ba2 is only applicable for densities 1gb. 5. an n is the most significant address bit for a given density and configuration. some larg- er address bits may be dont care during column addressing, depending on density and configuration. 512mb: x4, x8, x16 ddr2 sdram commands pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 69 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. 6. bank addresses (ba) determine which bank is to be operated upon. ba during a load mode command selects which mode register is programmed. 7. self refresh exit is asynchronous. 8. burst reads or writes at bl = 4 cannot be terminated or interrupted. see figure 47 (page 95) and figure 59 (page 106) for other restrictions and details. 9. the power-down mode does not perform any refresh operations. the duration of power- down is limited by the refresh requirements outlined in the ac parametric section. table 38: truth table C current state bank n C command to bank n notes: 1C6 apply to the entire table current state cs# ras# cas# we# command/action notes any h x x x deselect (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle l l h h activate (select and activate row) l l l h refresh 7 l l l l load mode 7 row active l h l h read (select column and start read burst) 8 l h l l write (select column and start write burst) 8 l l h l precharge (deactivate row in bank or banks) 9 read (auto precharge disabled) l h l h read (select column and start new read burst) 8 l h l l write (select column and start write burst) 8, 10 l l h l precharge (start precharge) 9 write (auto pre- charge disa- bled) l h l h read (select column and start read burst) 8 l h l l write (select column and start new write burst) 8 l l h l precharge (start precharge) 9 notes: 1. this table applies when cke n - 1 was high and cke n is high and after t xsnr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted (the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, t rp has been met, and any read burst is com- plete. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/ accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled and has not yet terminated. write: a write burst has been initiated with auto precharge disabled and has not yet terminated. 4. the following states must not be interrupted by a command issued to the same bank. issue deselect or nop commands, or allowable commands to the other bank, on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and this table, and according to table 39 (page 72). 512mb: x4, x8, x16 ddr2 sdram commands pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 70 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. precharge: starts with registration of a precharge command and ends when t rp is met. after t rp is met, the bank will be in the idle state. read with au- to precharge enabled: starts with registration of a read command with auto precharge ena- bled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. row activate: starts with registration of an activate command and ends when t rcd is met. after t rcd is met, the bank will be in the row active state. write with au- to precharge enabled: starts with registration of a write command with auto precharge ena- bled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. 5. the following states must not be interrupted by any executable command (deselect or nop commands must be applied on each positive clock edge during these states): refresh: starts with registration of a refresh command and ends when t rfc is met. after t rfc is met, the ddr2 sdram will be in the all banks idle state. accessing mode register: starts with registration of the load mode command and ends when t mrd has been met. after t mrd is met, the ddr2 sdram will be in the all banks idle state. precharge all: starts with registration of a precharge all command and ends when t rp is met. after t rp is met, all banks will be in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specific; requires that all banks are idle and bursts are not in progress. 8. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 9. may or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 10. a write command may be applied after the completion of the read burst. 512mb: x4, x8, x16 ddr2 sdram commands pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 71 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 39: truth table C current state bank n C command to bank m notes: 1C6 apply to the entire table current state cs# ras# cas# we# command/action notes any h x x x deselect (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle x x x x any command otherwise allowed to bank m row active, active, or precharge l l h h activate (select and activate row) l h l h read (select column and start read burst) 7 l h l l write (select column and start write burst) 7 l l h l precharge read (auto precharge disabled) l l h h activate (select and activate row) l h l h read (select column and start new read burst) 7 l h l l write (select column and start write burst) 7, 8 l l h l precharge write (auto pre- charge disabled) l l h h activate (select and activate row) l h l h read (select column and start read burst) 7, 9, 10 l h l l write (select column and start new write burst) 7 l l h l precharge read (with auto precharge) l l h h activate (select and activate row) l h l h read (select column and start new read burst) 7 l h l l write (select column and start write burst) 7, 8 l l h l precharge write (with auto precharge) l l h h activate (select and activate row) l h l h read (select column and start read burst) 7, 10 l h l l write (select column and start new write burst) 7 l l h l precharge notes: 1. this table applies when cke n - 1 was high and cke n is high and after t xsnr has been met (if the previous state was self refresh). 2. this table describes an alternate bank operation, except where noted (the current state is for bank n and the commands shown are those allowed to be issued to bank m , assum- ing that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, t rp has been met, and any read burst is complete. row active: a row in the bank has been activated and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated with auto precharge disabled and has not yet terminated. write: a write burst has been initiated with auto precharge disabled and has not yet terminated. 512mb: x4, x8, x16 ddr2 sdram commands pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 72 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. read with auto precharge enabled/ write with auto precharge enabled: the read with auto precharge enabled or write with auto pre- charge enabled states can each be broken into two parts: the access period and the precharge period. for read with auto pre- charge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible precharge command that still accesses all of the data in the burst. for write with auto precharge, the pre- charge period begins when t wr ends, with t wr measured as if auto precharge was disabled. the access period starts with regis- tration of the command and ends where the precharge period (or t rp) begins. this device supports concurrent auto precharge such that when a read with auto precharge is enabled or a write with auto precharge is enabled, any command to other banks is allowed, as long as that command does not interrupt the read or write data transfer already in process. in either case, all other related limitations apply (contention between read da- ta and write data must be avoided). the minimum delay from a read or write command with auto precharge enabled to a command to a different bank is summarized in table 40 (page 73). 4. refresh and load mode commands may only be issued when all banks are idle. 5. not used. 6. all states and sequences not shown are illegal or reserved. 7. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. a write command may be applied after the completion of the read burst. 9. requires appropriate dm. 10. the number of clock cycles required to meet t wtr is either two or t wtr/ t ck, whichever is greater. table 40: minimum delay with auto precharge enabled from command (bank n ) to command (bank m ) minimum delay (with concurrent auto precharge) units write with auto precharge read or read with auto precharge (cl - 1) + (bl/2) + t wtr t ck write or write with auto precharge (bl/2) t ck precharge or activate 1 t ck read with auto precharge read or read with auto precharge (bl/2) t ck write or write with auto precharge (bl/2) + 2 t ck precharge or activate 1 t ck deselect the deselect function (cs# high) prevents new commands from being executed by the ddr2 sdram. the ddr2 sdram is effectively deselected. operations already in progress are not affected. deselect is also referred to as command inhibit. 512mb: x4, x8, x16 ddr2 sdram commands pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 73 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. no operation (nop) the no operation (nop) command is used to instruct the selected ddr2 sdram to perform a nop (cs# is low; ras#, cas#, and we are high). this prevents unwanted commands from being registered during idle or wait states. operations already in pro- gress are not affected. load mode (lm) the mode registers are loaded via bank address and address inputs. the bank address balls determine which mode register will be programmed. see mode register (mr) (page 75). the lm command can only be issued when all banks are idle, and a subse- quent executable command cannot be issued until t mrd is met. activate the activate command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the bank address inputs determines the bank, and the address inputs select the row. this row remains active (or open) for accesses until a pre- charge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the bank address inputs determine the bank, and the address provided on address inputs a0Ca i (where a i is the most significant column address bit for a given configura- tion) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. ddr2 sdram also supports the al feature, which allows a read or write command to be issued prior to t rcd (min) by delaying the actual registration of the read/write command to the internal device by al clock cycles. write the write command is used to initiate a burst write access to an active row. the value on the bank select inputs selects the bank, and the address provided on inputs a0Ca i (where a i is the most significant column address bit for a given configuration) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be pre- charged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. ddr2 sdram also supports the al feature, which allows a read or write command to be issued prior to t rcd (min) by delaying the actual registration of the read/write command to the internal device by al clock cycles. input data appearing on the dq is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to memory; if the dm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location (see figure 64 (page 111)). 512mb: x4, x8, x16 ddr2 sdram commands pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 74 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row activation a specified time ( t rp) after the precharge command is issued, except in the case of concurrent auto precharge, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. after a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command is allowed if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. however, the precharge period will be determined by the last precharge command issued to the bank. refresh refresh is used during normal operation of the ddr2 sdram and is analogous to cas#- before-ras# (cbr) refresh. all banks must be in the idle mode prior to issuing a refresh command. this command is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a dont care during a refresh command. self refresh the self refresh command can be used to retain data in the ddr2 sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr2 sdram retains data without external clocking. all power supply inputs (including vref) must be maintained at valid levels upon entry/exit and during self refresh operation. the self refresh command is initiated like a refresh command except cke is low. the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh. mode register (mr) the mode register is used to define the specific mode of operation of the ddr2 sdram. this definition includes the selection of a burst length, burst type, cas latency, operat- ing mode, dll reset, write recovery, and power-down mode, as shown in figure 34 (page 76). contents of the mode register can be altered by re-executing the load mode (lm) command. if the user chooses to modify only a subset of the mr variables, all variables must be programmed when the command is issued. the mr is programmed via the lm command and will retain the stored information until it is programmed again or until the device loses power (except for bit m8, which is self-clearing). reprogramming the mode register will not alter the contents of the mem- ory array, provided it is performed correctly. the lm command can only be issued (or reissued) when all banks are in the precharged state (idle state) and no bursts are in progress. the controller must wait the specified time t mrd before initiating any subsequent operations such as an activate com- mand. violating either of these requirements will result in an unspecified operation. 512mb: x4, x8, x16 ddr2 sdram mode register (mr) pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 75 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. burst length burst length is defined by bits m0Cm2, as shown in figure 34. read and write accesses to the ddr2 sdram are burst-oriented, with the burst length being programmable to either four or eight. the burst length determines the maximum number of column loca- tions that can be accessed for a given read or write command. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a2Ca i when bl = 4 and by a3Ca i when bl = 8 (where a i is the most significant column address bit for a given configuration). the remaining (least signifi- cant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. figure 34: mr definition burst length cas# bt pd a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 6 5 4 3 8 2 1 0 a10 a12 a11 ba0 ba1 10 11 12 n 0 0 14 burst length reserved reserved 4 8 reserved reserved reserved reserved m0 0 1 0 1 0 1 0 1 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 0 1 burst type sequential interleaved m3 cas latency (cl) reserved reserved reserved 3 4 5 6 7 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 0 1 mode normal test m7 15 dll tm 0 1 dll reset no yes m8 write recovery reserved 2 3 4 5 6 7 8 m9 0 1 0 1 0 1 0 1 m10 0 0 1 1 0 0 1 1 m11 0 0 0 0 1 1 1 1 wr a n 2 mr m14 0 1 0 1 mode register definition mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) m15 0 0 1 1 m12 0 1 pd mode fast exit (normal) slow exit (low power) latency 16 ba2 1 notes: 1. m16 (ba2) is only applicable for densities 1gb, reserved for future use, and must be programmed to 0. 2. mode bits (m n ) with corresponding address balls (a n ) greater than m12 (a12) are re- served for future use and must be programmed to 0. 3. not all listed wr and cl options are supported in any individual speed grade. 512mb: x4, x8, x16 ddr2 sdram mode register (mr) pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 76 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. burst type accesses within a given burst may be programmed to be either sequential or inter- leaved. the burst type is selected via bit m3, as shown in figure 34. the ordering of accesses within a burst is determined by the burst length, the burst type, and the start- ing column address, as shown in table 41. ddr2 sdram supports 4-bit burst mode and 8-bit burst mode only. for 8-bit burst mode, full interleaved address ordering is supported; however, sequential address ordering is nibble-based. table 41: burst definition burst length starting column address (a2, a1, a0) order of accesses within a burst burst type = sequential burst type = interleaved 4 0 0 0, 1, 2, 3 0, 1, 2, 3 0 1 1, 2, 3, 0 1, 0, 3, 2 1 0 2, 3, 0, 1 2, 3, 0, 1 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 operating mode the normal operating mode is selected by issuing a command with bit m7 set to 0, and all other bits set to the desired values, as shown in figure 34 (page 76). when bit m7 is 1, no other bits of the mode register are programmed. programming bit m7 to 1 places the ddr2 sdram into a test mode that is only used by the manufacturer and should not be used. no operation or functionality is guaranteed if m7 bit is 1. dll reset dll reset is defined by bit m8, as shown in figure 34. programming bit m8 to 1 will activate the dll reset function. bit m8 is self-clearing, meaning it returns back to a value of 0 after the dll reset function has been issued. anytime the dll reset function is used, 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the t ac or t dqsck parameters. 512mb: x4, x8, x16 ddr2 sdram mode register (mr) pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 77 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. write recovery write recovery (wr) time is defined by bits m9Cm11, as shown in figure 34 (page 76). the wr register is used by the ddr2 sdram during write with auto precharge opera- tion. during write with auto precharge operation, the ddr2 sdram delays the inter- nal auto precharge operation by wr clocks (programmed in bits m9Cm11) from the last data burst. an example of write with auto precharge is shown in figure 63 (page 110). wr values of 2, 3, 4, 5, 6, 7, or 8 clocks may be used for programming bits m9Cm11. the user is required to program the value of wr, which is calculated by dividing t wr (in nanoseconds) by t ck (in nanoseconds) and rounding up a noninteger value to the next integer; wr (cycles) = t wr (ns)/ t ck (ns). reserved states should not be used as an un- known operation or incompatibility with future versions may result. power-down mode active power-down (pd) mode is defined by bit m12, as shown in figure 34. pd mode enables the user to determine the active power-down mode, which determines perform- ance versus power savings. pd mode bit m12 does not apply to precharge pd mode. when bit m12 = 0, standard active pd mode, or fast-exit active pd mode, is enabled. the t xard parameter is used for fast-exit active pd exit timing. the dll is expected to be enabled and running during this mode. when bit m12 = 1, a lower-power active pd mode, or slow-exit active pd mode, is enabled. the t xards parameter is used for slow-exit active pd exit timing. the dll can be enabled but frozen during active pd mode because the exit-to-read command timing is relaxed. the power difference expected between i dd3p normal and i dd3p low- power mode is defined in the ddr2 i dd specifications and conditions table. 512mb: x4, x8, x16 ddr2 sdram mode register (mr) pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 78 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. cas latency (cl) the cas latency (cl) is defined by bits m4Cm6, as shown in figure 34 (page 76). cl is the delay, in clock cycles, between the registration of a read command and the availa- bility of the first bit of output data. the cl can be set to 3, 4, 5, 6, or 7 clocks, depending on the speed grade option being used. ddr2 sdram does not support any half-clock latencies. reserved states should not be used as an unknown operation otherwise incompatibility with future versions may result. ddr2 sdram also supports a feature called posted cas additive latency (al). this fea- ture allows the read command to be issued prior to t rcd (min) by delaying the internal command to the ddr2 sdram by al clocks. the al feature is described in further detail in posted cas additive latency (al) (page 82). examples of cl = 3 and cl = 4 are shown in figure 35; both assume al = 0. if a read command is registered at clock edge n , and the cl is m clocks, the data will be available nominally coincident with clock edge n + m (this assumes al = 0). figure 35: cl do n + 3 do n + 2 do n + 1 ck ck# command dq dqs, dqs# cl = 3 (al = 0) read t0 t1 t2 dont care transitioning data nop nop nop do n t3 t4 t5 nop nop t6 nop do n + 3 do n + 2 do n + 1 ck ck# command dq dqs, dqs# cl = 4 (al = 0) read t0 t1 t2 nop nop nop do n t3 t4 t5 nop nop t6 nop notes: 1. bl = 4. 2. posted cas# additive latency (al) = 0. 3. shown with nominal t ac, t dqsck, and t dqsq. 512mb: x4, x8, x16 ddr2 sdram mode register (mr) pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 79 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. extended mode register (emr) the extended mode register controls functions beyond those controlled by the mode register; these additional functions are dll enable/disable, output drive strength, on- die termination (odt), posted al, off-chip driver impedance calibration (ocd), dqs# enable/disable, rdqs/rdqs# enable/disable, and output disable/enable. these func- tions are controlled via the bits shown in figure 36. the emr is programmed via the lm command and will retain the stored information until it is programmed again or the device loses power. reprogramming the emr will not alter the contents of the memory array, provided it is performed correctly. the emr must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any subsequent opera- tion. violating either of these requirements could result in an unspecified operation. figure 36: emr definition dll posted cas# r tt out a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 9 7 6 5 4 3 8 2 1 0 a10 a12 ba0 ba1 10 11 12 n 0 14 e1 0 1 output drive strength full reduced posted cas# additive latency (al) 3 0 1 2 3 4 5 6 reserved e3 0 1 0 1 0 1 0 1 e4 0 0 1 1 0 0 1 1 e5 0 0 0 0 1 1 1 1 0 1 dll enable enable (normal) disable (test/debug) e0 15 e11 0 1 rdqs enable no yes ocd program a n 2 ods r tt dqs# e10 0 1 dqs# enable enable disable rdqs r tt (nominal) r tt disabled 75 150 50 e2 0 1 0 1 e6 0 0 1 1 0 1 outputs enabled disabled e12 0 1 0 1 mode register set mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) e15 0 0 1 1 e14 mrs ba2 1 16 0 ocd operation 4 ocd exit reserved reserved reserved enable ocd defaults e7 0 1 0 0 1 e8 0 0 1 0 1 e9 0 0 0 1 1 notes: 1. e16 (ba2) is only applicable for densities 1gb, reserved for future use, and must be pro- grammed to 0. 2. mode bits (e n ) with corresponding address balls (a n ) greater than e12 (a12) are re- served for future use and must be programmed to 0. 3. not all listed al options are supported in any individual speed grade. 4. as detailed in the initialization (page 86) section notes, during initialization of the ocd operation, all three bits must be set to 1 for the ocd default state, then set to 0 before initialization is finished. 512mb: x4, x8, x16 ddr2 sdram extended mode register (emr) pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 80 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. dll enable/disable the dll may be enabled or disabled by programming bit e0 during the lm command, as shown in figure 36 (page 80). these specifications are applicable when the dll is enabled for normal operation. dll enable is required during power-up initialization and upon returning to normal operation after having disabled the dll for the purpose of debugging or evaluation. enabling the dll should always be followed by resetting the dll using the lm command. the dll is automatically disabled when entering self refresh operation and is auto- matically re-enabled and reset upon exit of self refresh operation. anytime the dll is enabled (and subsequently reset), 200 clock cycles must occur be- fore a read command can be issued to allow time for the internal clock to synchronize with the external clock. failing to wait for synchronization to occur may result in a viola- tion of the t ac or t dqsck parameters. anytime the dll is disabled and the device is operated below 25 mhz, any auto re- fresh command should be followed by a precharge all command. output drive strength the output drive strength is defined by bit e1, as shown in figure 36. the normal drive strength for all outputs is specified to be sstl_18. programming bit e1 = 0 selects nor- mal (full strength) drive strength for all outputs. selecting a reduced drive strength option (e1 = 1) will reduce all outputs to approximately 45 to 60 percent of the sstl_18 drive strength. this option is intended for the support of lighter load and/or point-to- point environments. dqs# enable/disable the dqs# ball is enabled by bit e10. when e10 = 0, dqs# is the complement of the differential data strobe pair dqs/dqs#. when disabled (e10 = 1), dqs is used in a single- ended mode and the dqs# ball is disabled. when disabled, dqs# should be left float- ing; however, it may be tied to ground via a 20 to 10k resistor. this function is also used to enable/disable rdqs#. if rdqs is enabled (e11 = 1) and dqs# is enabled (e10 = 0), then both dqs# and rdqs# will be enabled. rdqs enable/disable the rdqs ball is enabled by bit e11, as shown in figure 36. this feature is only applica- ble to the x8 configuration. when enabled (e11 = 1), rdqs is identical in function and timing to data strobe dqs during a read. during a write operation, rdqs is ignored by the ddr2 sdram. output enable/disable the output enable function is defined by bit e12, as shown in figure 36. when ena- bled (e12 = 0), all outputs (dq, dqs, dqs#, rdqs, rdqs#) function normally. when disabled (e12 = 1), all outputs (dq, dqs, dqs#, rdqs, rdqs#) are disabled, thus remov- ing output buffer current. the output disable feature is intended to be used during i dd characterization of read current. 512mb: x4, x8, x16 ddr2 sdram extended mode register (emr) pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 81 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. on-die termination (odt) odt effective resistance, r tt(eff) , is defined by bits e2 and e6 of the emr, as shown in figure 36 (page 80). the odt feature is designed to improve signal integrity of the mem- ory channel by allowing the ddr2 sdram controller to independently turn on/off odt for any or all devices. r tt effective resistance values of 50, 75, and 150 are selecta- ble and apply to each dq, dqs/dqs#, rdqs/rdqs#, udqs/udqs#, ldqs/ldqs#, dm, and udm/ldm signals. bits (e6, e2) determine what odt resistance is enabled by turning on/off sw1, sw2, or sw3. the odt effective resistance value is selected by enabling switch sw1, which enables all r1 values that are 150 each, enabling an ef- fective resistance of 75 (r tt2 [eff] = r2/2). similarly, if sw2 is enabled, all r2 values that are 300 each, enable an effective odt resistance of 150 (r tt2[eff] = r2/2). switch sw3 enables r1 values of 100, enabling effective resistance of 50. reserved states should not be used, as an unknown operation or incompatibility with future ver- sions may result. the odt control ball is used to determine when r tt(eff) is turned on and off, assuming odt has been enabled via bits e2 and e6 of the emr. the odt feature and odt input ball are only used during active, active power-down (both fast-exit and slow-exit modes), and precharge power-down modes of operation. odt must be turned off prior to entering self refresh mode. during power-up and initi- alization of the ddr2 sdram, odt should be disabled until the emr command is issued. this will enable the odt feature, at which point the odt ball will determine the r tt(eff) value. anytime the emr enables the odt function, odt may not be driven high until eight clocks after the emr has been enabled (see figure 79 (page 127) for odt timing diagrams). off-chip driver (ocd) impedance calibration the off-chip driver function is an optional ddr2 jedec feature not supported by micron and thereby must be set to the default state. enabling ocd beyond the default settings will alter the i/o drive characteristics and the timing and output i/o specifica- tions will no longer be valid (see initialization (page 86) for proper setting of ocd defaults). posted cas additive latency (al) posted cas additive latency (al) is supported to make the command and data bus effi- cient for sustainable bandwidths in ddr2 sdram. bits e3Ce5 define the value of al, as shown in figure 36. bits e3Ce5 allow the user to program the ddr2 sdram with an al of 0, 1, 2, 3, 4, 5, or 6 clocks. reserved states should not be used as an unknown opera- tion or incompatibility with future versions may result. in this operation, the ddr2 sdram allows a read or write command to be issued prior to t rcd (min) with the requirement that al t rcd (min). a typical application using this feature would set al = t rcd (min) - 1 t ck. the read or write command is held for the time of the al before it is issued internally to the ddr2 sdram device. rl is controlled by the sum of al and cl; rl = al + cl. write latency (wl) is equal to rl minus one clock; wl = al + cl - 1 t ck. an example of rl is shown in figure 37 (page 83). an example of a wl is shown in figure 38 (page 83). 512mb: x4, x8, x16 ddr2 sdram extended mode register (emr) pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 82 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 37: read latency do n + 3 do n + 2 do n + 1 ck ck# command dq dqs, dqs# al = 2 active n t0 t1 t2 dont care transitioning data read n nop nop do n t3 t4 t5 nop t6 nop t7 t8 nop nop cl = 3 rl = 5 t rcd (min) nop notes: 1. bl = 4. 2. shown with nominal t ac, t dqsck, and t dqsq. 3. rl = al + cl = 5. figure 38: write latency ck ck# command dq dqs, dqs# active n t0 t1 t2 dont care transitioning data nop nop t3 t4 t5 nop t6 nop di n + 3 di n + 2 di n + 1 wl = al + cl - 1 = 4 t7 nop di n t rcd (min) nop al = 2 cl - 1 = 2 write n notes: 1. bl = 4. 2. cl = 3. 3. wl = al + cl - 1 = 4. 512mb: x4, x8, x16 ddr2 sdram extended mode register (emr) pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 83 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. extended mode register 2 (emr2) the extended mode register 2 (emr2) controls functions beyond those controlled by the mode register. currently all bits in emr2 are reserved, except for e7, which is used in commercial or high-temperature operations, as shown in figure 39. the emr2 is pro- grammed via the lm command and will retain the stored information until it is program- med again or until the device loses power. reprogramming the emr will not alter the contents of the memory array, provided it is performed correctly. bit e7 (a7) must be programmed as 1 to provide a faster refresh rate on it and at devices if t c exceeds 85c. emr2 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any subsequent opera- tion. violating either of these requirements could result in an unspecified operation. figure 39: emr2 definition a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 9 7 6 5 4 3 8 2 1 0 a10 a12 a11 ba0 ba1 10 11 12 n 0 14 15 a n 2 e14 0 1 0 1 mode register set mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) e15 0 0 1 1 mrs 0 0 0 0 0 srt 0 0 0 0 0 0 0 ba2 1 16 0 e7 0 1 srt enable 1x refresh rate (0c to 85c) 2x refresh rate (>85c) notes: 1. e16 (ba2) is only applicable for densities 1gb, reserved for future use, and must be pro- grammed to 0. 2. mode bits (e n ) with corresponding address balls (a n ) greater than e12 (a12) are re- served for future use and must be programmed to 0. 512mb: x4, x8, x16 ddr2 sdram extended mode register 2 (emr2) pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 84 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. extended mode register 3 (emr3) the extended mode register 3 (emr3) controls functions beyond those controlled by the mode register. currently all bits in emr3 are reserved, as shown in figure 40. the emr3 is programmed via the lm command and will retain the stored information until it is programmed again or until the device loses power. reprogramming the emr will not alter the contents of the memory array, provided it is performed correctly. emr3 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any subsequent opera- tion. violating either of these requirements could result in an unspecified operation. figure 40: emr3 definition e14 0 1 0 1 mode register set mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) e15 0 0 1 1 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 9 7 6 5 4 3 8 2 1 0 a10 a12 a11 ba0 ba1 10 11 12 n 0 14 15 a n 2 mrs 0 0 0 0 0 0 0 0 0 0 0 0 0 ba2 1 16 0 notes: 1. e16 (ba2) is only applicable for densities 1gb, is reserved for future use, and must be programmed to 0. 2. mode bits (e n ) with corresponding address balls (a n ) greater than e12 (a12) are re- served for future use and must be programmed to 0. 512mb: x4, x8, x16 ddr2 sdram extended mode register 3 (emr3) pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 85 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. initialization figure 41: ddr2 power-up and initialization ddr2 sdram must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in unde- fined operation. figure 41 illustrates, and the notes outline, the sequence required for power-up and initialization. t vtd 1 cke r tt power-up: v dd and stable clock (ck, ck#) t = 200s (min) 3 high-z dm 15 dqs 15 high-z address 16 ck ck# t cl v tt 1 v ref v ddq command nop 3 pre t0 ta0 dont care t cl t ck v dd odt dq 15 high-z tb0 200 cycles of ck are required before a read command can be issued mr with dll reset t rfc lm 8 pre 9 lm 7 ref 10 ref 10 lm 11 tg0 th0 ti0 tj0 mr without dll reset emr with ocd default tk0 tl0 tm0 te0 tf0 emr(2) emr(3) t mrd lm 6 lm 5 a10 = 1 t rpa tc0 td0 sstl_18 low level 2 valid 14 valid indicates a break in time scale lm 12 emr with ocd exit lm 13 normal operation see no te 10 code code a10 = 1 code code code code code t mrd t mrd t mrd t mrd t rpa t rfc v ddl t mrd t mrd emr t = 400ns (min) 4 lvcmos low level 2 512mb: x4, x8, x16 ddr2 sdram initialization pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 86 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. notes: 1. applying power; if cke is maintained below 0.2 v ddq , outputs remain disabled. to guarantee r tt (odt resistance) is off, v ref must be valid and a low level must be applied to the odt ball (all other inputs may be undefined; i/os and outputs must be less than v ddq during voltage ramp time to avoid ddr2 sdram device latch-up). v tt is not ap- plied directly to the device; however, t vtd should be 0 to avoid device latch-up. at least one of the following two sets of conditions (a or b) must be met to obtain a stable supply state (stable supply defined as v dd , v ddl , v ddq , v ref , and v tt are between their minimum and maximum values as stated in table 13 (page 42)): a. single power source: the v dd voltage ramp from 300mv to v dd,min must take no lon- ger than 200ms; during the v dd voltage ramp, |v dd - v ddq | 0.3v. once supply voltage ramping is complete (when v ddq crosses v dd,min ), table 13 specifications apply. ? v dd , v ddl , and v ddq are driven from a single power converter output ? v tt is limited to 0.95v max ? v ref tracks v ddq /2; v ref must be within 0.3v with respect to v ddq /2 during supply ramp time; does not need to be satisfied when ramping power down ? v ddq v ref at all times b. multiple power sources: v dd v ddl v ddq must be maintained during supply voltage ramping, for both ac and dc levels, until supply voltage ramping completes (v ddq crosses v dd,min ). once supply voltage ramping is complete, table 13 specifications apply. ? apply v dd and v ddl before or at the same time as v ddq ; v dd /v ddl voltage ramp time must be 200ms from when v dd ramps from 300mv to v dd,min ? apply v ddq before or at the same time as v tt ; the v ddq voltage ramp time from when v dd,min is achieved to when v ddq,min is achieved must be 500ms; while v dd is ramp- ing, current can be supplied from v dd through the device to v ddq ? v ref must track v ddq /2; v ref must be within 0.3v with respect to v ddq /2 during sup- ply ramp time; v ddq v ref must be met at all times; does not need to be satisfied when ramping power down ? apply v tt ; the v tt voltage ramp time from when v ddq,min is achieved to when v tt,min is achieved must be no greater than 500ms 2. cke requires lvcmos input levels prior to state t0 to ensure dqs are high-z during de- vice power-up prior to v ref being stable. after state t0, cke is required to have sstl_18 input levels. once cke transitions to a high level, it must stay high for the duration of the initialization sequence. 3. for a minimum of 200s after stable power and clock (ck, ck#), apply nop or deselect commands, then take cke high. 4. wait a minimum of 400ns then issue a precharge all command. 5. issue a load mode command to the emr(2). to issue an emr(2) command, provide low to ba0, and provide high to ba1; set register e7 to 0 or 1 to select appropri- ate self refresh rate; remaining emr(2) bits must be 0 (see extended mode register 2 (emr2) (page 84) for all emr(2) requirements). 6. issue a load mode command to the emr(3). to issue an emr(3) command, provide high to ba0 and ba1; remaining emr(3) bits must be 0. extended mode register 3 (emr3) for all emr(3) requirements. 7. issue a load mode command to the emr to enable dll. to issue a dll enable com- mand, provide low to ba1 and a0; provide high to ba0; bits e7, e8, and e9 can be set to 0 or 1; micron recommends setting them to 0; remaining emr bits must be 0. extended mode register (emr) (page 80) for all emr requirements. 8. issue a load mode command to the mr for dll reset. 200 cycles of clock input is re- quired to lock the dll. to issue a dll reset, provide high to a8 and provide low to ba1 and ba0; cke must be high the entire time the dll is resetting; remaining mr bits must be 0. mode register (mr) (page 75) for all mr requirements. 9. issue precharge all command. 512mb: x4, x8, x16 ddr2 sdram initialization pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 87 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. 10. issue two or more refresh commands. 11. issue a load mode command to the mr with low to a8 to initialize device operation (that is, to program operating parameters without resetting the dll). to access the mr, set ba0 and ba1 low; remaining mr bits must be set to desired settings. mode register (mr) (page 75) for all mr requirements. 12. issue a load mode command to the emr to enable ocd default by setting bits e7, e8, and e9 to 1, and then setting all other desired parameters. to access the emr, set ba0 high and ba1 low (see extended mode register (emr) (page 80) for all emr require- ments. 13. issue a load mode command to the emr to enable ocd exit by setting bits e7, e8, and e9 to 0, and then setting all other desired parameters. to access the extended mode registers, emr, set ba0 high and ba1 low for all emr requirements. 14. the ddr2 sdram is now initialized and ready for normal operation 200 clock cycles af- ter the dll reset at tf0. 15. dm represents dm for the x4, x8 configurations and udm, ldm for the x16 configura- tion; dqs represents dqs, dqs#, udqs, udqs#, ldqs, ldqs#, rdqs, rdqs# for the appropriate configuration (x4, x8, x16); dq represents dq0Cdq3 for x4, dqCdq7 for x8 and dq0Cdq15 for x16. 16. a10 = precharge all, code = desired values for mode registers (bank addresses are required to be decoded). 512mb: x4, x8, x16 ddr2 sdram initialization pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 88 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. activate before any read or write commands can be issued to a bank within the ddr2 sdram, a row in that bank must be opened (activated), even when additive latency is used. this is accomplished via the activate command, which selects both the bank and the row to be activated. after a row is opened with an activate command, a read or write command may be issued to that row subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the activate command on which a read or write command can be entered. the same procedure is used to convert other specification limits from time units to clock cycles. for example, a t rcd (min) specification of 20ns with a 266 mhz clock ( t ck = 3.75ns) results in 5.3 clocks, rounded up to 6. this is shown in figure 42, which covers any case where 5 < t rcd (min)/ t ck 6. figure 42 also shows the case for t rrd where 2 < t rrd (min)/ t ck 3. figure 42: example: meeting t rrd (min) and t rcd (min) command dont care t1 t0 t2 t3 t4 t5 t6 t7 t rrd t rrd row row col bank x bank y row bank z bank y nop act nop nop act nop nop rd/wr t rcd ck# address bank address ck t8 t9 nop nop a subsequent activate command to a different row in the same bank can only be is- sued after the previous active row has been closed (precharged). the minimum time interval between successive activate commands to the same bank is defined by t rc. a subsequent activate command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the mini- mum time interval between successive activate commands to different banks is defined by t rrd. ddr2 devices with 8 banks (1gb or larger) have an additional requirement: t faw. this requires no more than four activate commands may be issued in any given t faw (min) period, as shown in figure 43 (page 90). 512mb: x4, x8, x16 ddr2 sdram activate pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 89 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 43: multibank activate restriction command dont care t1 t0 t2 t3 t4 t5 t6 t7 t rrd (min) row row read act act nop t f a w (min) bank address ck# address ck t8 t9 col bank a act read read read act nop row col row col col bank c bank b bank d bank c bank e act row t10 bank d bank b bank a note: 1. ddr2-533 (-37e, x4 or x8), t ck = 3.75ns, bl = 4, al = 3, cl = 4, t rrd (min) = 7.5ns, t faw (min) = 37.5ns. 512mb: x4, x8, x16 ddr2 sdram activate pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 90 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. read read bursts are initiated with a read command. the starting column and bank ad- dresses are provided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is automatically precharged at the completion of the burst. if auto precharge is disabled, the row will be left open after the completion of the burst. during read bursts, the valid data-out element from the starting column address will be available read latency (rl) clocks later. rl is defined as the sum of al and cl: rl = al + cl. the value for al and cl are programmable via the mr and emr com- mands, respectively. each subsequent data-out element will be valid nominally at the next positive or negative clock edge (at the next crossing of ck and ck#). figure 44 (page 92) shows examples of rl based on different al and cl settings. dqs/dqs# is driven by the ddr2 sdram along with output data. the initial low state on dqs and the high state on dqs# are known as the read preamble ( t rpre). the low state on dqs and the high state on dqs# coincident with the last data-out ele- ment are known as the read postamble ( t rpst). upon completion of a burst, assuming no other commands have been initiated, the dq will go high-z. a detailed explanation of t dqsq (valid data-out skew), t qh (data-out window hold), and the valid data window are depicted in figure 53 (page 100) and fig- ure 54 (page 101). a detailed explanation of t dqsck (dqs transition skew to ck) and t ac (data-out transition skew to ck) is shown in figure 55 (page 102). data from any read burst may be concatenated with data from a subsequent read command to provide a continuous flow of data. the first data element from the new burst follows the last element of a completed burst. the new read command should be issued x cycles after the first read command, where x equals bl/2 cycles (see fig- ure 45 (page 93)). nonconsecutive read data is illustrated in figure 46 (page 94). full-speed random read accesses within a page (or pages) can be performed. ddr2 sdram supports the use of concurrent auto precharge timing (see table 42 (page 97)). ddr2 sdram does not allow interrupting or truncating of any read burst using bl = 4 operations. once the bl = 4 read command is registered, it must be allowed to com- plete the entire read burst. however, a read (with auto precharge disabled) using bl = 8 operation may be interrupted and truncated only by another read burst as long as the interruption occurs on a 4-bit boundary due to the 4 n prefetch architecture of ddr2 sdram. as shown in figure 47 (page 95), read burst bl = 8 operations may not be interrupted or truncated with any other command except another read com- mand. data from any read burst must be completed before a subsequent write burst is al- lowed. an example of a read burst followed by a write burst is shown in figure 48 (page 95). the t dqss (nom) case is shown ( t dqss [min] and t dqss [max] are de- fined in figure 56 (page 104)). 512mb: x4, x8, x16 ddr2 sdram read pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 91 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 44: read latency read nop nop nop nop nop bank a , col n ck ck# command address dq dqs, dqs# do n do n t0 t1 t2 t3 t4n t5n t4 t5 ck ck# command read nop nop nop nop nop address bank a, col n rl = 3 (al = 0, cl = 3) dq dqs, dqs# do n t0 t1 t2 t3 t3n t4n t4 t5 ck ck# command read nop nop nop nop nop address bank a, col n rl = 4 (al = 0, cl = 4) dq dqs, dqs# t0 t1 t2 t3 t3n t4n t4 t5 al = 1 cl = 3 rl = 4 (al = 1 + cl = 3) dont care transitioning data notes: 1. do n = data-out from column n . 2. bl = 4. 3. three subsequent elements of data-out appear in the programmed order following do n . 4. shown with nominal t ac, t dqsck, and t dqsq. 512mb: x4, x8, x16 ddr2 sdram read pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 92 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 45: consecutive read bursts ck ck# command read nop read nop nop nop nop address bank, col n bank, col b command read nop read nop nop nop address bank, col n bank, col b rl = 3 ck ck# dq dqs, dqs# rl = 4 dq dqs, dqs# do n do b do n do b t0 t1 t2 t3 t3n t4n t4 t5 t6 t5n t6n t0 t1 t2 t3 t2n nop t3n t4n t4 t5 t6 t5n t6n dont care transitioning data t ccd t ccd notes: 1. do n (or b ) = data-out from column n (or column b ). 2. bl = 4. 3. three subsequent elements of data-out appear in the programmed order following do n . 4. three subsequent elements of data-out appear in the programmed order following do b . 5. shown with nominal t ac, t dqsck, and t dqsq. 6. example applies only when read commands are issued to same device. 512mb: x4, x8, x16 ddr2 sdram read pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 93 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 46: nonconsecutive read bursts command read nop nop nop nop nop nop nop read t0 t1 t2 t3 t3n t4 t5 t7 t8 t6 t4n t6n t7n ck ck# t5 t7 t8 t5n t6 t4n t7n command nop nop nop nop read nop nop nop read t0 t1 t2 t3 t4 dq do n do b dont care transitioning data address bank, col n bank, col b address bank, col n bank, col b ck ck# cl = 4 cl = 3 dq do n do b dqs, dqs# dqs, dqs# notes: 1. do n (or b ) = data-out from column n (or column b ). 2. bl = 4. 3. three subsequent elements of data-out appear in the programmed order following do n . 4. three subsequent elements of data-out appear in the programmed order following do b . 5. shown with nominal t ac, t dqsck, and t dqsq. 6. example applies when read commands are issued to different devices or nonconsecu- tive reads. 512mb: x4, x8, x16 ddr2 sdram read pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 94 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 47: read interrupted by read t0 t1 t2 dont care transitioning data t3 t4 t5 t6 command read 1 nop 2 nop 2 valid valid valid read 3 valid valid valid t7 t8 t9 ck ck# cl = 3 (al = 0) t ccd address v alid 4 v alid 4 cl = 3 (al = 0) dq do do do do do do do do do do do do a10 v alid 5 dqs, dqs# notes: 1. bl = 8 required; auto precharge must be disabled (a10 = low). 2. nop or command inhibit commands are valid. precharge command cannot be is- sued to banks used for reads at t0 and t2. 3. interrupting read command must be issued exactly 2 t ck from previous read. 4. read command can be issued to any valid bank and row address (read command at t0 and t2 can be either same bank or different bank). 5. auto precharge can be either enabled (a10 = high) or disabled (a10 = low) by the in- terrupting read command. 6. example shown uses al = 0; cl = 3, bl = 8, shown with nominal t ac, t dqsck, and t dqsq. figure 48: read-to-write ck ck# t0 t1 t2 dont care transitioning data t3 t4 t5 t6 t7 t8 t9 t10 t11 al = 2 cl = 3 rl = 5 wl = rl - 1 = 4 t rcd = 3 command act n nop nop nop nop nop nop read n nop nop nop write dqs, dqs# dq do n do n + 1 do n + 2 do n + 3 di n di n + 1 di n + 2 di n + 3 notes: 1. bl = 4; cl = 3; al = 2. 2. shown with nominal t ac, t dqsck, and t dqsq. read with precharge a read burst may be followed by a precharge command to the same bank, provided auto precharge is not activated. the minimum read-to-precharge command spac- ing to the same bank has two requirements that must be satisfied: al + bl/2 clocks and t rtp. t rtp is the minimum time from the rising clock edge that initiates the last 4-bit prefetch of a read command to the precharge command. for bl = 4, this is the time from the actual read (al after the read command) to precharge command. for bl = 8, this is the time from al + 2 ck after the read-to-precharge command. following the precharge command, a subsequent command to the same bank can- 512mb: x4, x8, x16 ddr2 sdram read pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 95 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. not be issued until t rp is met. however, part of the row precharge time is hidden during the access of the last data elements. examples of read-to-precharge for bl = 4 are shown in figure 49 and in figure 50 for bl = 8. the delay from read-to-precharge period to the same bank is al + bl/ 2 - 2ck + max ( t rtp/ t ck or 2 ck) where max means the larger of the two. figure 49: read-to-precharge C bl = 4 ck ck# t0 t1 t2 dont care transitioning data t3 t4 t5 t6 t7 address bank a bank a bank a t ras (min) t rtp (min) t rp (min) al + bl/2 - 2ck + max ( t rtp/ t ck or 2ck) command read nop pre act nop nop nop nop 4-bit prefetch dq do do do do a10 valid valid cl = 3 al = 1 dqs, dqs# t rc (min) notes: 1. rl = 4 (al = 1, cl = 3); bl = 4. 2. t rtp 2 clocks. 3. shown with nominal t ac, t dqsck, and t dqsq. figure 50: read-to-precharge C bl = 8 ck ck# t0 t1 t2 dont care transitioning data t3 t4 t5 t6 t7 t8 cl = 3 al = 1 dqs, dqs# first 4-bit prefetch second 4-bit prefetch t rtp (min) t rp (min) address bank a bank a bank a t rc (min) t ras (min) a10 valid valid al + bl/2 - 2ck + max ( t rtp/ t ck or 2ck) dq do do do do do do do do command read nop nop nop nop nop nop act pre notes: 1. rl = 4 (al = 1, cl = 3); bl = 8. 2. t rtp 2 clocks. 3. shown with nominal t ac, t dqsck, and t dqsq. 512mb: x4, x8, x16 ddr2 sdram read pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 96 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. read with auto precharge if a10 is high when a read command is issued, the read with auto precharge function is engaged. the ddr2 sdram starts an auto precharge operation on the rising clock edge that is al + (bl/2) cycles later than the read with auto precharge command provi- ded t ras (min) and t rtp are satisfied. if t ras (min) is not satisfied at this rising clock edge, the start point of the auto precharge operation will be delayed until t ras (min) is satisfied. if t rtp (min) is not satisfied at this rising clock edge, the start point of the auto precharge operation will be delayed until t rtp (min) is satisfied. when the inter- nal precharge is pushed out by t rtp, t rp starts at the point where the internal pre- charge happens (not at the next rising clock edge after this event). when bl = 4, the minimum time from read with auto precharge to the next activate command is al + ( t rtp + t rp)/ t ck. when bl = 8, the minimum time from read with auto precharge to the next activate command is al + 2 clocks + ( t rtp + t rp)/ t ck. the term ( t rtp + t rp)/ t ck is always rounded up to the next integer. a general purpose equa- tion can also be used: al + bl/2 - 2ck + ( t rtp + t rp)/ t ck. in any event, the internal precharge does not start earlier than two clocks after the last 4-bit prefetch. read with auto precharge command may be applied to one bank while another bank is operational. this is referred to as concurrent auto precharge operation, as noted in ta- ble 42. examples of read with precharge and read with auto precharge with applica- ble timing requirements are shown in figure 51 (page 98) and figure 52 (page 99), respectively. table 42: read using concurrent auto precharge from command (bank n ) to command (bank m ) minimum delay (with concurrent auto precharge) units read with auto precharge read or read with auto precharge bl/2 t ck write or write with auto precharge (bl/2) + 2 t ck precharge or activate 1 t ck 512mb: x4, x8, x16 ddr2 sdram read pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 97 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 51: bank read C without auto precharge ck ck# cke a10 bank address t ck t ch t cl ra t rcd t ras 3 t rc t rp cl = 3 dm t0 t1 t2 t3 t4 t5 t7n t8n t6 t7 t8 dq 8 dqs, dqs# case 1: t ac (min) and t dqsck (min) case 2: t ac (max) and t dqsck (max) dq 8 dqs, dqs# t rpre t rpre t rpst t dqsck (min) t lz (min) t lz (max) t ac (min) t lz (min) do n t hz (max) t ac (max) t lz (min) do n nop 1 nop 1 command act ra col n pre 3 bank x ra ra bank x bank x 6 7 7 7 7 act bank x nop 1 nop 1 nop 1 nop 1 t hz (min) one bank all banks dont care transitioning data read 2 address 5 t rtp 4 t rpst t dqsck (max) t9 notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4 and al = 0 in the case shown. 3. the precharge command can only be applied at t6 if t ras (min) is met. 4. read-to-precharge = al + bl/2 - 2ck + max ( t rtp/ t ck or 2ck). 5. disable auto precharge. 6. dont care if a10 is high at t5. 7. i/o balls, when entering or exiting high-z, are not referenced to a specific voltage level, but to when the device begins to drive or no longer drives, respectively. 8. do n = data-out from column n ; subsequent elements are applied in the programmed order. 512mb: x4, x8, x16 ddr2 sdram read pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 98 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 52: bank read C with auto precharge 4-bit prefetch ck ck# cke a10 bank address t ck t ch t cl ra t rcd t ras t rc t rp cl = 3 dm t0 t1 t2 t3 t4 t5 t7n t8n t6 t7 t8 dq 6 dqs, dqs# case 1: t ac (min) and t dqsck (min) case 2: t ac (max) and t dqsck (max) dq 6 dqs, dqs# t rpre t rpre t rpst t rpst t dqsck (min) t dqsck (max) t lz (min) t lz (max) t ac (min) t lz (min) t hz (max) t ac (max) t lz (max) do n nop 1 nop 1 command 1 act ra col n bank x ra ra bank x act bank x nop 1 nop 1 nop 1 nop 1 nop 1 t hz (min) dont care transitioning data read 2,3 address al = 1 t rtp internal precharge 4 5 5 5 5 do n notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4, rl = 4 (al = 1, cl = 3) in the case shown. 3. the ddr2 sdram internally delays auto precharge until both t ras (min) and t rtp (min) have been satisfied. 4. enable auto precharge. 5. i/o balls, when entering or exiting high-z, are not referenced to a specific voltage level, but to when the device begins to drive or no longer drives, respectively. 6. do n = data-out from column n ; subsequent elements are applied in the programmed order. 512mb: x4, x8, x16 ddr2 sdram read pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 99 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 53: x4, x8 data output timing C t dqsq, t qh, and data valid window dq (last data valid) dq 4 dq 4 dq 4 dq 4 dq 4 dq 4 dqs# dqs 3 dq (last data valid) dq (first data no longer valid) dq (first data no longer valid) all dqs and dqs collectively 6 earliest signal transition latest signal transition t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n ck ck# t1 t2 t3 t4 t2n t3n t qh 5 t hp 1 t hp 1 t hp 1 t qh 5 t qhs t qh 5 t hp 1 t hp 1 t hp 1 t qh 5 t dqsq 2 t dqsq 2 t dqsq 2 t dqsq 2 data valid window data valid window data valid window data valid window t qhs t qhs t qhs notes: 1. t hp is the lesser of t cl or t ch clock transitions collectively when a bank is active. 2. t dqsq is derived at each dqs clock edge, is not cumulative over time, begins with dqs transitions, and ends with the last valid transition of dq. 3. dq transitioning after the dqs transition defines the t dqsq window. dqs transitions at t2 and at t2n are early dqs, at t3 are nominal dqs, and at t3n are late dqs. 4. dq0, dq1, dq2, dq3 for x4 or dq0Cdq7 for x8. 5. t qh is derived from t hp: t qh = t hp - t qhs. 6. the data valid window is derived for each dqs transition and is defined as t qh - t dqsq. 512mb: x4, x8, x16 ddr2 sdram read pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 100 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 54: x16 data output timing C t dqsq, t qh, and data valid window dq (last data valid) 4 dq 4 dq 4 dq 4 dq 4 dq 4 dq 4 ldsq# ldqs 3 dq (last data valid) 4 dq (first data no longer valid) 4 dq (first data no longer valid) 4 dq0Cdq7 and ldqs collectively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n ck ck# t1 t2 t3 t4 t2n t3n t qh 5 t qh 5 t dqsq 2 t dqsq 2 t dqsq 2 t dqsq 2 data valid window data valid window dq (last data valid) 7 dq 7 dq 7 dq 7 dq 7 dq 7 dq 7 udqs# udqs 3 dq (last data valid) 7 dq (first data no longer valid) 7 dq (first data no longer valid) 7 dq8Cdq15 and udqs collectively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n t qh 5 t qh 5 t qh 5 t qh 5 t dqsq 2 t dqsq 2 t dqsq 2 t dqsq 2 t hp 1 t hp 1 t hp 1 t hp 1 t hp 1 t hp 1 t qh 5 t qh 5 data valid window data valid window data valid window data valid window data valid window upper byte lower byte data valid window t qhs t qhs t qhs t qhs t qhs t qhs t qhs t qhs notes: 1. t hp is the lesser of t cl or t ch clock transitions collectively when a bank is active. 2. t dqsq is derived at each dqs clock edge, is not cumulative over time, begins with dqs transitions, and ends with the last valid transition of dq. 3. dq transitioning after the dqs transitions define the t dqsq window. ldqs defines the lower byte, and udqs defines the upper byte. 4. dq0, dq1, dq2, dq3, dq4, dq5, dq6, or dq7. 512mb: x4, x8, x16 ddr2 sdram read pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 101 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. 5. t qh is derived from t hp: t qh = t hp - t qhs. 6. the data valid window is derived for each dqs transition and is t qh - t dqsq. 7. dq8, dq9, dq10, d11, dq12, dq13, dq14, or dq15. figure 55: data output timing C t ac and t dqsck ck ck# dqs#/dqs or ldqs#/ldqs/udq#/udqs 3 t0 1 t1 t2 t3 t3n t4 t4n t5 t5n t6 t6n t7 t rpst t dqsck 2 (min) t dqsck 2 (max) dq (last data valid) dq (first data valid) all dqs collectively 4 t ac 5 (min) t ac 5 (max) t lz (min) t hz (max) t3 t3 t3n t4n t5n t6n t3n t3n t4n t4n t5n t5n t6n t6n t4 t5 t5 t6 t6 t3 t4 t5 t6 t4 t hz (max) t lz (min) t rpre notes: 1. read command with cl = 3, al = 0 issued at t0. 2. t dqsck is the dqs output window relative to ck and is the long-term component of dqs skew. 3. dq transitioning after dqs transitions define t dqsq window. 4. all dq must transition by t dqsq after dqs transitions, regardless of t ac. 5. t ac is the dq output window relative to ck and is the long term component of dq skew. 6. t lz (min) and t ac (min) are the first valid signal transitions. 7. t hz (max) and t ac (max) are the latest valid signal transitions. 8. i/o balls, when entering or exiting high-z, are not referenced to a specific voltage level, but to when the device begins to drive or no longer drives, respectively. write write bursts are initiated with a write command. ddr2 sdram uses wl equal to rl minus one clock cycle (wl = rl - 1ck) (see read (page 74)). the starting column and bank addresses are provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. note: for the write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element will be registered on the first rising edge of dqs following the write command, and subsequent data elements will be reg- istered on successive edges of dqs. the low state on dqs between the write com- mand and the first rising edge is known as the write preamble; the low state on dqs following the last data-in element is known as the write postamble. the time between the write command and the first rising dqs edge is wl t dqss. subsequent dqs positive rising edges are timed, relative to the associated clock edge, as t dqss. t dqss is specified with a relatively wide range (25% of one clock cycle). all of 512mb: x4, x8, x16 ddr2 sdram write pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 102 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. the write diagrams show the nominal case, and where the two extreme cases ( t dqss [min] and t dqss [max]) might not be intuitive, they have also been included. figure 56 (page 104) shows the nominal case and the extremes of t dqss for bl = 4. upon comple- tion of a burst, assuming no other commands have been initiated, the dq will remain high-z and any additional input data will be ignored. data for any write burst may be concatenated with a subsequent write command to provide continuous flow of input data. the first data element from the new burst is ap- plied after the last element of a completed burst. the new write command should be issued x cycles after the first write command, where x equals bl/2. figure 57 (page 105) shows concatenated bursts of bl = 4 and how full-speed random write accesses within a page or pages can be performed. an example of nonconsecutive writes is shown in figure 58 (page 105). ddr2 sdram supports concurrent auto pre- charge options, as shown in table 43. ddr2 sdram does not allow interrupting or truncating any write burst using bl = 4 operation. once the bl = 4 write command is registered, it must be allowed to com- plete the entire write burst cycle. however, a write bl = 8 operation (with auto precharge disabled) might be interrupted and truncated only by another write burst as long as the interruption occurs on a 4-bit boundary due to the 4 n -prefetch architec- ture of ddr2 sdram. write burst bl = 8 operations may not be interrupted or truncated with any command except another write command, as shown in figure 59 (page 106). data for any write burst may be followed by a subsequent read command. to follow a write, t wtr should be met, as shown in figure 60 (page 107). the number of clock cycles required to meet t wtr is either 2 or t wtr/ t ck, whichever is greater. data for any write burst may be followed by a subsequent precharge command. t wr must be met, as shown in figure 61 (page 108). t wr starts at the end of the data burst, regard- less of the data mask condition. table 43: write using concurrent auto precharge from command (bank n ) to command (bank m ) minimum delay (with concurrent auto precharge) units write with auto precharge read or read with auto precharge (cl - 1) + (bl/2) + t wtr t ck write or write with auto precharge (bl/2) t ck precharge or activate 1 t ck 512mb: x4, x8, x16 ddr2 sdram write pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 103 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 56: write burst dqs, dqs# t dqss (max) t dqss (nom) t dqss (min) dm dq ck ck# command write nop nop address bank a , col b nop nop t0 t1 t2 t3 t2n t4 t3n dqs, dqs# 5 dm dq dqs, dqs# dm dq di b di b di b dont care transitioning data t dqss 5 wl t dqss wl - t dqss t dqss 5 wl + t dqss notes: 1. subsequent rising dqs signals must align to the clock within t dqss. 2. di b = data-in for column b . 3. three subsequent elements of data-in are applied in the programmed order following di b . 4. shown with bl = 4, al = 0, cl = 3; thus, wl = 2. 5. a10 is low with the write command (auto precharge is disabled). 512mb: x4, x8, x16 ddr2 sdram write pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 104 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 57: consecutive write-to-write ck ck# command write nop write nop nop nop address bank, col b nop bank, col n t0 t1 t2 t3 t2n t4 t5 t4n t6 t5n t3n t1n dq dqs, dqs# dm di n di b dont care transitioning data wl t dqss t dqss (nom) wl = 2 t ccd wl = 2 1 1 1 notes: 1. subsequent rising dqs signals must align to the clock within t dqss. 2. di b , etc. = data-in for column b , etc. 3. three subsequent elements of data-in are applied in the programmed order following di b . 4. three subsequent elements of data-in are applied in the programmed order following di n . 5. shown with bl = 4, al = 0, cl = 3; thus, wl = 2. 6. each write command may be to any bank. figure 58: nonconsecutive write-to-write ck ck# command write nop nop nop nop nop address bank, col b write bank, col n t0 t1 t2 t3 t2n t4 t5 t4n t3n t5n t6 t6n dq dqs, dqs# dm di n di b t dqss (nom) wl t dqss dont care transitioning data wl = 2 wl = 2 1 1 1 notes: 1. subsequent rising dqs signals must align to the clock within t dqss. 2. di b (or n ), etc. = data-in for column b (or column n ). 3. three subsequent elements of data-in are applied in the programmed order following di b . 4. three subsequent elements of data-in are applied in the programmed order following di n . 5. shown with bl = 4, al = 0, cl = 3; thus, wl = 2. 6. each write command may be to any bank. 512mb: x4, x8, x16 ddr2 sdram write pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 105 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 59: write interrupted by write ck ck# command dq dqs, dqs# wl = 3 write 1 a t0 t1 t2 dont care transitioning data di a t3 t4 t5 t6 write 3 b di b t7 t8 t9 wl = 3 2-clock requirement address a10 valid 6 valid 5 valid 5 valid 4 valid 4 v alid 4 nop 2 nop 2 nop 2 nop 2 nop 2 7 7 7 7 7 di a + 1 di a + 3 di a + 2 di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 notes: 1. bl = 8 required and auto precharge must be disabled (a10 = low). 2. the nop or command inhibit commands are valid. the precharge command cannot be issued to banks used for writes at t0 and t2. 3. the interrupting write command must be issued exactly 2 t ck from previous write. 4. the earliest write-to-precharge timing for write at t0 is wl + bl/2 + t wr where t wr starts with t7 and not t5 (because bl = 8 from mr and not the truncated length). 5. the write command can be issued to any valid bank and row address (write command at t0 and t2 can be either same bank or different bank). 6. auto precharge can be either enabled (a10 = high) or disabled (a10 = low) by the in- terrupting write command. 7. subsequent rising dqs signals must align to the clock within t dqss. 8. example shown uses al = 0; cl = 4, bl = 8. 512mb: x4, x8, x16 ddr2 sdram write pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 106 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 60: write-to-read t dqss (nom) ck ck# command write nop nop nop nop nop nop nop address bank a , col b bank a , col n read t0 t1 t2 t3 t2n t4 t5 t9n t3n t6 t7 t8 t9 t wtr 1 cl = 3 cl = 3 cl = 3 dq dqs, dqs# dm di b t dqss (min) dq dqs, dqs# dm di b t dqss (max) dq dqs, dqs# dm di b di di dont care transitioning data wl t dqss wl - t dqss wl + t dqss nop di 2 2 2 notes: 1. t wtr is required for any read following a write to the same device, but it is not re- quired between module ranks. 2. subsequent rising dqs signals must align to the clock within t dqss. 3. di b = data-in for column b ; do n = data-out from column n . 4. bl = 4, al = 0, cl = 3; thus, wl = 2. 5. one subsequent element of data-in is applied in the programmed order following di b . 6. t wtr is referenced from the first positive ck edge after the last data-in pair. 7. a10 is low with the write command (auto precharge is disabled). 8. the number of clock cycles required to meet t wtr is either 2 or t wtr/ t ck, whichever is greater. 512mb: x4, x8, x16 ddr2 sdram write pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 107 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 61: write-to-precharge t dqss (nom) ck ck# command write nop nop nop nop nop address bank a , col b bank, ( a or all ) nop t0 t1 t2 t3 t2n t4 t5 t3n t6 t7 t wr t rp dq dqs# dqs dm di b t dqss (min) dq dqs# dqs dm di b t dqss (max) dq dqs# dqs dm di b dont care transitioning data wl + t dqss wl - t dqss wl + t dqss pre 1 1 1 notes: 1. subsequent rising dqs signals must align to the clock within t dqss. 2. di b = data-in for column b . 3. three subsequent elements of data-in are applied in the programmed order following di b . 4. bl = 4, cl = 3, al = 0; thus, wl = 2. 5. t wr is referenced from the first positive ck edge after the last data-in pair. 6. the precharge and write commands are to the same bank. however, the precharge and write commands may be to different banks, in which case t wr is not required and the precharge command could be applied earlier. 7. a10 is low with the write command (auto precharge is disabled). 512mb: x4, x8, x16 ddr2 sdram write pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 108 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 62: bank write C without auto precharge ck ck# cke a10 t ck t ch t cl ra t rcd t ras t rp t wr t0 t1 t2 t3 t5 t6 t6n t7 t8 t9 t5n nop 1 nop 1 command 3 5 act ra col n write 2 nop 1 one bank all banks bank x pre bank x nop 1 nop 1 nop 1 t dqsl t dqsh t wpst bank x 4 dq 6 dm di n dont care transitioning data wl t dqss (nom) t wpre dqs, dqs# address nop 1 wl = 2 t4 bank select notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4 and al = 0 in the case shown. 3. disable auto precharge. 4. dont care if a10 is high at t9. 5. subsequent rising dqs signals must align to the clock within t dqss. 6. di n = data-in for column n ; subsequent elements are applied in the programmed order. 7. t dsh is applicable during t dqss (min) and is referenced from ck t5 or t6. 8. t dss is applicable during t dqss (max) and is referenced from ck t6 or t7. 512mb: x4, x8, x16 ddr2 sdram write pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 109 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 63: bank write C with auto precharge ck ck# cke a10 bank select t ck t ch t cl ra t rcd t ras t rp wr 4 t0 t1 t2 t3 t4 t5 t5n t6 t7 t8 t6n nop 1 nop 1 command 3 act ra col n write 2 nop 1 bank x nop 1 bank x nop 1 nop 1 nop 1 t dqsl t dqsh t wpst dq 6 dm wl t dqss (nom) dont care transitioning data t wpre dqs, dqs# address t9 nop 1 wl = 2 di n 5 notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4 and al = 0 in the case shown. 3. enable auto precharge. 4. wr is programmed via mr9Cmr11 and is calculated by dividing t wr (in ns) by t ck and rounding up to the next integer value. 5. subsequent rising dqs signals must align to the clock within t dqss. 6. di n = data-in from column n ; subsequent elements are applied in the programmed order. 7. t dsh is applicable during t dqss (min) and is referenced from ck t5 or t6. 8. t dss is applicable during t dqss (max) and is referenced from ck t6 or t7. 512mb: x4, x8, x16 ddr2 sdram write pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 110 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 64: write C dm operation ck ck# cke a10 bank select t ck t ch t cl ra t rcd t ras t rpa t wr 5 t0 t1 t2 t3 t4 t5 t7n t6 t7 t8 t6n nop 1 nop 1 command 3 act ra col n write 2 nop 1 one bank all banks bank x bank x nop 1 nop 1 nop 1 nop 1 nop 1 nop 1 t dqsl t dqsh t wpst bank x 4 dq 7 dm dont care transitioning data wl t dqss (nom) t wpre pre dqs, dqs# address t9 t10 t11 al = 1 wl = 2 di n 6 notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4, al = 1, and wl = 2 in the case shown. 3. disable auto precharge. 4. dont care if a10 is high at t11. 5. t wr starts at the end of the data burst regardless of the data mask condition. 6. subsequent rising dqs signals must align to the clock within t dqss. 7. di n = data-in for column n ; subsequent elements are applied in the programmed order. 8. t dsh is applicable during t dqss (min) and is referenced from ck t6 or t7. 9. t dss is applicable during t dqss (max) and is referenced from ck t7 or t8. 512mb: x4, x8, x16 ddr2 sdram write pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 111 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 65: data input timing dqs dqs# t dqsh t wpst t dqsl t dss 2 t dsh 1 t dsh 1 t dss 2 dm dq ck ck# t1 t0 t1n t2 t2n t3 t4 t3n di dont care transitioning data t wpre 3 wl - t dqss (nom) notes: 1. t dsh (min) generally occurs during t dqss (min). 2. t dss (min) generally occurs during t dqss (max). 3. subsequent rising dqs signals must align to the clock within t dqss. 4. write command issued at t0. 5. for x16, ldqs controls the lower byte and udqs controls the upper byte. 6. write command with wl = 2 (cl = 3, al = 0) issued at t0. precharge precharge can be initiated by either a manual precharge command or by an autopre- charge in conjunction with either a read or write command. precharge will deacti- vate the open row in a particular bank or the open row in all banks. the precharge operation is shown in the previous read and write operation sections. during a manual precharge command, the a10 input determines whether one or all banks are to be precharged. in the case where only one bank is to be precharged, bank address inputs determine the bank to be precharged. when all banks are to be pre- charged, the bank address inputs are treated as dont care. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. when a single-bank pre- charge command is issued, t rp timing applies. when the precharge (all) com- mand is issued, t rpa timing applies, regardless of the number of banks opened. 512mb: x4, x8, x16 ddr2 sdram precharge pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 112 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. refresh the commercial temperature ddr2 sdram requires refresh cycles at an average in- terval of 7.8125s (max) and all rows in all banks must be refreshed at least once every 64ms. the refresh period begins when the refresh command is registered and ends t rfc (min) later. the average interval must be reduced to 3.9s (max) when t c ex- ceeds +85c. figure 66: refresh mode ck ck# command nop 1 nop 1 nop 1 pre cke ra address a10 bank bank(s) 3 ba ref nop 1 ref 2 nop 1 act nop 1 one bank all banks t ck t ch t cl ra dq 4 dm 4 dqs, dqs# 4 t rfc 2 t rp t rfc (min) t0 t1 t2 t3 t4 ta0 tb0 ta1 tb1 tb2 dont care indicates a break in time scale notes: 1. nop commands are shown for ease of illustration; other valid commands may be possi- ble at these times. cke must be active during clock positive transitions. 2. the second refresh is not required and is only shown as an example of two back-to- back refresh commands. 3. dont care if a10 is high at this point; a10 must be high if more than one bank is active (must precharge all active banks). 4. dm, dq, and dqs signals are all dont care/high-z for operations shown. 512mb: x4, x8, x16 ddr2 sdram refresh pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 113 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. self refresh the self refresh command is initiated when cke is low. the differential clock should remain stable and meet t cke specifications at least 1 t ck after entering self refresh mode. the procedure for exiting self refresh requires a sequence of commands. first, the differential clock must be stable and meet t ck specifications at least 1 t ck prior to cke going back to high. once cke is high ( t cke [min] has been satisfied with three clock registrations), the ddr2 sdram must have nop or deselect com- mands issued for t xsnr. a simple algorithm for meeting both refresh and dll require- ments is used to apply nop or deselect commands for 200 clock cycles before applying any other command. 512mb: x4, x8, x16 ddr2 sdram self refresh pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 114 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 67: self refresh ck 1 ck# command nop ref address cke 1 valid dq dm dqs#, dqs nop 4 t rp 8 t ch t cl t ck 1 t ck 1 t xsnr 2, 5, 10 t isxr 2 enter self refresh mode (synchronous) exit self refresh mode (asynchronous) t0 t1 ta2 ta1 dont care ta0 tc0 tb0 t xsrd 2, 7 valid 5 nop 4 t cke (min) 9 t2 odt 6 t aofd/ t aofpd 6 td0 valid 7 valid 5 indicates a break in time scale t ih t ih t cke 3 notes: 1. clock must be stable and meeting t ck specifications at least 1 t ck after entering self refresh mode and at least 1 t ck prior to exiting self refresh mode. 2. self refresh exit is asynchronous; however, t xsnr and t xsrd timing starts at the first ris- ing clock edge where cke high satisfies t isxr. 3. cke must stay high until t xsrd is met; however, if self refresh is being re-entered, cke may go back low after t xsnr is satisfied. 4. nop or deselect commands are required prior to exiting self refresh until state tc0, which allows any nonread command. 5. t xsnr is required before any nonread command can be applied. 6. odt must be disabled and r tt off ( t aofd and t aofpd have been satisfied) prior to enter- ing self refresh at state t1. 7. t xsrd (200 cycles of ck) is required before a read command can be applied at state td0. 8. device must be in the all banks idle state prior to entering self refresh mode. 9. after self refresh has been entered, t cke (min) must be satisfied prior to exiting self refresh. 10. upon exiting self refresh, odt must remain low until t xsrd is satisfied. 512mb: x4, x8, x16 ddr2 sdram self refresh pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 115 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. power-down mode ddr2 sdram supports multiple power-down modes that allow significant power sav- ings over normal operating modes. cke is used to enter and exit different power-down modes. power-down entry and exit timings are shown in figure 68 (page 117). detailed power-down entry conditions are shown in figure 69 (page 119)Cfigure 76 (page 122). table 44 (page 118) is the cke truth table. ddr2 sdram requires cke to be registered high (active) at all times that an access is in progressfrom the issuing of a read or write command until completion of the burst. thus, a clock suspend is not supported. for reads, a burst completion is defined when the read postamble is satisfied; for writes, a burst completion is defined when the write postamble and t wr (write-to-precharge command) or t wtr (write-to- read command) are satisfied, as shown in figure 71 (page 120) and figure 72 (page 120) on figure 72 (page 120). the number of clock cycles required to meet t wtr is either two or t wtr/ t ck, whichever is greater. power-down mode (see figure 68 (page 117)) is entered when cke is registered low coincident with an nop or deselect command. cke is not allowed to go low during a mode register or extended mode register command time, or while a read or write operation is in progress. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down. if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deac- tivates the input and output buffers, excluding ck, ck#, odt, and cke. for maximum power savings, the dll is frozen during precharge power-down. exiting active power- down requires the device to be at the same voltage and frequency as when it entered power-down. exiting precharge power-down requires the device to be at the same volt- age as when it entered power-down; however, the clock frequency is allowed to change (see precharge power-down clock frequency change (page 123)). the maximum duration for either active or precharge power-down is limited by the re- fresh requirements of the device t rfc (max). the minimum duration for power-down entry and exit is limited by the t cke (min) parameter. the following must be main- tained while in power-down mode: cke low, a stable clock signal, and stable power supply signals at the inputs of the ddr2 sdram. all other input signals are dont care except odt. detailed odt timing diagrams for different power-down modes are shown in figure 81 (page 128)Cfigure 86 (page 132). the power-down state is synchronously exited when cke is registered high (in con- junction with a nop or deselect command), as shown in figure 68 (page 117). 512mb: x4, x8, x16 ddr2 sdram power-down mode pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 116 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 68: power-down ck ck# command nop nop nop address cke dq dm dqs, dqs# valid t ch t cl enter power-down mode 6 exit power-down mode dont care t cke (min) 2 t cke (min) 2 valid valid 1 valid t xp 3 , t xard 4 t xards 5 valid valid t is t ih t ih t1 t2 t3 t4 t5 t6 t7 t8 t ck notes: 1. if this command is a precharge (or if the device is already in the idle state), then the power-down mode shown is precharge power-down. if this command is an activate (or if at least one row is already active), then the power-down mode shown is active power- down. 2. t cke (min) of three clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the three clocks of registration. thus, after any cke transition, cke may not transition from its valid level during the time period of t is + 2 t ck + t ih. cke must not transition during its t is and t ih window. 3. t xp timing is used for exit precharge power-down and active power-down to any non- read command. 4. t xard timing is used for exit active power-down to read command if fast exit is selec- ted via mr (bit 12 = 0). 5. t xards timing is used for exit active power-down to read command if slow exit is selec- ted via mr (bit 12 = 1). 6. no column accesses are allowed to be in progress at the time power-down is entered. if the dll was not in a locked state when cke went low, the dll must be reset after exiting power-down mode for proper read operation. 512mb: x4, x8, x16 ddr2 sdram power-down mode pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 117 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. table 44: truth table C cke notes 1C4 apply to the entire table current state cke command ( n ) cs#, ras#, cas#, we# action ( n ) notes previous cycle ( n - 1) current cycle ( n ) power-down l l x maintain power-down 5, 6 l h deselect or nop power-down exit 7, 8 self refresh l l x maintain self refresh 6 l h deselect or nop self refresh exit 7, 9, 10 bank(s) active h l deselect or nop active power-down entry 7, 8, 11, 12 all banks idle h l deselect or nop precharge power-down entry 7, 8, 11 h l refresh self refresh entry 10, 12, 13 h h shown in table 37 (page 69) 14 notes: 1. cke ( n ) is the logic state of cke at clock edge n ; cke ( n - 1) was the state of cke at the previous clock edge. 2. current state is the state of the ddr2 sdram immediately prior to clock edge n . 3. command ( n ) is the command registered at clock edge n , and action ( n ) is a result of command ( n ). 4. the state of odt does not affect the states described in this table. the odt function is not available during self refresh (see odt timing (page 126) for more details and specif- ic restrictions). 5. power-down modes do not perform any refresh operations. the duration of power- down mode is therefore limited by the refresh requirements. 6. x means dont care (including floating around v ref ) in self refresh and power- down. however, odt must be driven high or low in power-down if the odt function is enabled via emr. 7. all states and sequences not shown are illegal or reserved unless explicitly described else- where in this document. 8. valid commands for power-down entry and exit are nop and deselect only. 9. on self refresh exit, deselect or nop commands must be issued on every clock edge occurring during the t xsnr period. read commands may be issued only after t xsrd (200 clocks) is satisfied. 10. valid commands for self refresh exit are nop and deselect only. 11. power-down and self refresh can not be entered while read or write operations, load mode operations, or precharge operations are in progress. see self refresh (page 114) and self refresh (page 75) for a list of detailed restrictions. 12. minimum cke high time is t cke = 3 t ck. minimum cke low time is t cke = 3 t ck. this requires a minimum of 3 clock cycles of registration. 13. self refresh mode can only be entered from the all banks idle state. 14. must be a legal command, as defined in table 37 (page 69). 512mb: x4, x8, x16 ddr2 sdram power-down mode pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 118 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 69: read-to-power-down or self refresh entry do ck ck# command dq dqs, dqs# rl = 3 t0 t1 t2 dont care transitioning data nop nop t3 t4 t5 valid t6 t7 t cke (min) address a10 nop cke read valid powe r -down 2 or self refresh entry nop 1 valid do do do notes: 1. in the example shown, read burst completes at t5; earliest power-down or self refresh entry is at t6. 2. power-down or self refresh entry may occur after the read burst completes. figure 70: read with auto precharge-to-power-down or self refresh entry ck ck# command dq dqs, dqs# rl = 3 t0 t1 t2 dont care transitioning data nop nop t3 t4 t5 valid valid t6 t7 t cke (min) address a10 nop cke read valid powe r -down or self refresh 2 entry nop 1 do do do do notes: 1. in the example shown, read burst completes at t5; earliest power-down or self refresh entry is at t6. 2. power-down or self refresh entry may occur after the read burst completes. 512mb: x4, x8, x16 ddr2 sdram power-down mode pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 119 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 71: write-to-power-down or self refresh entry ck ck# command dq dqs, dqs# wl = 3 t0 t1 t2 dont care transitioning data nop nop do t3 t4 t5 valid valid t6 valid t7 t8 t cke (min) address a10 nop write valid power-down or self refresh entry 1 t wtr nop 1 do do do cke note: 1. power-down or self refresh entry may occur after the write burst completes. figure 72: write with auto precharge-to-power-down or self refresh entry ck ck# command dq dqs, dqs# wl = 3 t0 t1 t2 dont care transitioning data nop nop do t3 t4 t5 valid valid ta0 valid 1 nop ta1 ta2 t cke (min) address a10 nop cke write valid power-down or self refresh entry wr 2 do do do indicates a break in time scale notes: 1. internal precharge occurs at ta0 when wr has completed; power-down entry may oc- cur 1 x t ck later at ta1, prior to t rp being satisfied. 2. wr is programmed through mr9Cmr11 and represents ( t wr [min] ns/ t ck) rounded up to next integer t ck. 512mb: x4, x8, x16 ddr2 sdram power-down mode pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 120 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 73: refresh command-to-power-down entry ck ck# command dont care t0 t1 valid refresh t2 t3 t cke (min) cke power-down 1 entry 1 x t ck nop note: 1. the earliest precharge power-down entry may occur is at t2, which is 1 t ck after the refresh command. precharge power-down entry occurs prior to t rfc (min) being satis- fied. figure 74: activate command-to-power-down entry ck ck# command dont care t0 t1 valid act t2 nop t3 t cke (min) cke power-down 1 entry 1 t ck address valid note: 1. the earliest active power-down entry may occur is at t2, which is 1 t ck after the acti- vate command. active power-down entry occurs prior to t rcd (min) being satisfied. 512mb: x4, x8, x16 ddr2 sdram power-down mode pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 121 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 75: precharge command-to-power-down entry ck ck# command dont care t0 t1 valid pre t2 nop t3 t cke (min) cke power-down 1 entry 1 x t ck address a10 valid all banks vs single bank note: 1. the earliest precharge power-down entry may occur is at t2, which is 1 t ck after the precharge command. precharge power-down entry occurs prior to t rp (min) being sat- isfied. figure 76: load mode command-to-power-down entry ck ck# command dont care t0 t1 valid lm t2 nop t3 t4 t cke (min) cke powe r -down 3 entry t mrd address valid 1 t rp 2 nop notes: 1. valid address for lm command includes mr, emr, emr(2), and emr(3) registers. 2. all banks must be in the precharged state and t rp met prior to issuing lm command. 3. the earliest precharge power-down entry is at t3, which is after t mrd is satisfied. 512mb: x4, x8, x16 ddr2 sdram power-down mode pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 122 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. precharge power-down clock frequency change when the ddr2 sdram is in precharge power-down mode, odt must be turned off and cke must be at a logic low level. a minimum of two differential clock cycles must pass after cke goes low before clock frequency may change. the device input clock frequency is allowed to change only within minimum and maximum operating frequen- cies specified for the particular speed grade. during input clock frequency change, odt and cke must be held at stable low levels. when the input clock frequency is changed, new stable clocks must be provided to the device before precharge power-down may be exited, and dll must be reset via mr after precharge power-down exit. depending on the new clock frequency, additional lm commands might be required to adjust the cl, wr, al, and so forth. depending on the new clock frequency, an additional lm com- mand might be required to appropriately set the wr mr9, mr10, mr11. during the dll relock period of 200 cycles, odt must remain off. after the dll lock time, the dram is ready to operate with a new clock frequency. figure 77: input clock frequency change during precharge power-down mode ck ck# command valid 4 nop address cke dq dm dqs, dqs# nop t ck enter precharge power-down mode exit precharge power-down mode t0 t1 t3 ta0 t2 dont care valid t cke (min) 3 t xp lm dll reset valid valid nop t ch t cl ta1 ta2 tb0 ta3 2 x t ck (min) 1 1 x t ck (min) 2 t ch t cl t ck odt 200 x t ck nop ta4 previous clock frequency new clock frequency frequency change indicates a break in time scale high-z high-z t cke (min) 3 notes: 1. a minimum of 2 t ck is required after entering precharge power-down prior to chang- ing clock frequencies. 2. when the new clock frequency has changed and is stable, a minimum of 1 t ck is re- quired prior to exiting precharge power-down. 512mb: x4, x8, x16 ddr2 sdram precharge power-down clock frequency change pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 123 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. 3. minimum cke high time is t cke = 3 t ck. minimum cke low time is t cke = 3 t ck. this requires a minimum of three clock cycles of registration. 4. if this command is a precharge (or if the device is already in the idle state), then the power-down mode shown is precharge power-down, which is required prior to the clock frequency change. reset cke low anytime ddr2 sdram applications may go into a reset state anytime during normal operation. if an application enters a reset condition, cke is used to ensure the ddr2 sdram de- vice resumes normal operation after reinitializing. all data will be lost during a reset condition; however, the ddr2 sdram device will continue to operate properly if the following conditions outlined in this section are satisfied. the reset condition defined here assumes all supply voltages (v dd , v ddq , v ddl , and v ref ) are stable and meet all dc specifications prior to, during, and after the reset op- eration. all other input balls of the ddr2 sdram device are a dont care during reset with the exception of cke. if cke asynchronously drops low during any valid operation (including a read or write burst), the memory controller must satisfy the timing parameter t delay before turning off the clocks. stable clocks must exist at the ck, ck# inputs of the dram be- fore cke is raised high, at which time the normal initialization sequence must occur (see initialization). the ddr2 sdram device is now ready for normal operation after the initialization sequence. figure 78 (page 125) shows the proper sequence for a re- set operation. 512mb: x4, x8, x16 ddr2 sdram reset pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 124 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 78: reset function cke r tt bank address high-z dm 3 dqs 3 high-z address a10 ck ck# t cl command nop 2 pre all banks ta0 dont care transitioning data t rpa t cl t ck odt dq 3 high-z t = 400ns (min) tb0 read nop 2 t0 t1 t2 col n bank a t delay 1 do do read nop 2 col n bank b high-z high-z unknown r tt on system reset t3 t4 t5 start of normal 5 initialization sequence nop 2 indicates a break in time scale 4 t cke (min) do notes: 1. v dd , v ddl , v ddq , v tt , and v ref must be valid at all times. 2. either nop or deselect command may be applied. 3. dm represents dm for x4/x8 configuration and udm, ldm for x16 configuration. dqs represents dqs, dqs#, udqs, udqs#, ldqs, ldqs#, rdqs, and rdqs# for the appropri- ate configuration (x4, x8, x16). 4. in certain cases where a read cycle is interrupted, cke going high may result in the completion of the burst. 5. initialization timing is shown in figure 41 (page 86). 512mb: x4, x8, x16 ddr2 sdram reset pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 125 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. odt timing once a 12ns delay ( t mod) has been satisfied, and after the odt function has been ena- bled via the emr load mode command, odt can be accessed under two timing categories. odt will operate either in synchronous mode or asynchronous mode, de- pending on the state of cke. odt can switch anytime except during self refresh mode and a few clocks after being enabled via emr, as shown in figure 79 (page 127). there are two timing categories for odtturn-on and turn-off. during active mode (cke high) and fast-exit power-down mode (any row of any bank open, cke low, mr[12 = 0]), t aond, t aon, t aofd, and t aof timing parameters are applied, as shown in figure 81 (page 128). during slow-exit power-down mode (any row of any bank open, cke low, mr[12] = 1) and precharge power-down mode (all banks/rows precharged and idle, cke low), t aonpd and t aofpd timing parameters are applied, as shown in figure 82 (page 129). odt turn-off timing, prior to entering any power-down mode, is determined by the pa- rameter t anpd (min), as shown in figure 83 (page 129). at state t2, the odt high signal satisfies t anpd (min) prior to entering power-down mode at t5. when t anpd (min) is satisfied, t aofd and t aof timing parameters apply. figure 83 (page 129) also shows the example where t anpd (min) is not satisfied because odt high does not occur until state t3. when t anpd (min) is not satisfied, t aofpd timing parameters apply. odt turn-on timing prior to entering any power-down mode is determined by the pa- rameter t anpd, as shown in figure 84 (page 130). at state t2, the odt high signal satisfies t anpd (min) prior to entering power-down mode at t5. when t anpd (min) is satisfied, t aond and t aon timing parameters apply. figure 84 (page 130) also shows the example where t anpd (min) is not satisfied because odt high does not occur until state t3. when t anpd (min) is not satisfied, t aonpd timing parameters apply. odt turn-off timing after exiting any power-down mode is determined by the parame- ter t axpd (min), as shown in figure 85 (page 131). at state ta1, the odt low signal satisfies t axpd (min) after exiting power-down mode at state t1. when t axpd (min) is satisfied, t aofd and t aof timing parameters apply. figure 85 (page 131) also shows the example where t axpd (min) is not satisfied because odt low occurs at state ta0. when t axpd (min) is not satisfied, t aofpd timing parameters apply. odt turn-on timing after exiting either slow-exit power-down mode or precharge power- down mode is determined by the parameter t axpd (min), as shown in figure 86 (page 132). at state ta1, the odt high signal satisfies t axpd (min) after exiting power- down mode at state t1. when t axpd (min) is satisfied, t aond and t aon timing parameters apply. figure 86 (page 132) also shows the example where t axpd (min) is not satisfied because odt high occurs at state ta0. when t axpd (min) is not satisfied, t aonpd timing parameters apply. 512mb: x4, x8, x16 ddr2 sdram odt timing pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 126 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 79: odt timing for entering and exiting power-down mode t anpd (3 t cks) first cke latched low t axpd (8 t cks) first cke latched high synchronous applicable modes applicable timing parameters synchronous synchronous or asynchronous any mode except self refresh mode any mode except self refresh mode active power-down fast (synchronous) active power-down slow (asynchronous) precharge power-down (asynchronous) t aond/ t aofd (synchronous) t aonpd/ t aofpd (asynchronous) t aond/ t aofd t aond/ t aofd cke 512mb: x4, x8, x16 ddr2 sdram odt timing pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 127 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. mrs command to odt update delay during normal operation, the value of the effective termination resistance can be changed with an emrs set command. t mod (max) updates the r tt setting. figure 80: timing for mrs command to odt update delay ck# ck odt 2 internal r tt setting emrs 1 nop nop nop nop nop command t mod old setting undefined new setting 0ns 2 t is t aofd indicates a break in time scale t0 ta0 ta1 ta2 ta3 ta4 ta5 notes: 1. the lm command is directed to the mode register, which updates the information in emr (a6, a2), that is, r tt (nominal). 2. to prevent any impedance glitch on the channel, the following conditions must be met: t aofd must be met before issuing the lm command; odt must remain low for the entire duration of the t mod window until t mod is met. figure 81: odt timing for active or fast-exit power-down mode t1 t0 t2 t3 t4 t5 t6 valid valid valid valid valid valid valid ck# ck odt r tt t aof (max) t aon (min) t aond address t aofd t aon (max) t aof (min) valid valid valid valid valid valid valid command t ch t cl dont care r tt unknown r tt on t ck cke 512mb: x4, x8, x16 ddr2 sdram odt timing pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 128 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 82: odt timing for slow-exit or precharge power-down modes dont care t1 t0 t2 t3 t4 t5 t6 valid valid valid valid valid valid valid ck# ck cke odt address valid valid valid valid valid valid valid command t ch t cl t aonpd (min) t aonpd (max) t aofpd (min) t aofpd (max) t ransitioning r tt t7 valid valid r tt unknown r tt on t ck r tt figure 83: odt turn-off timings when entering power-down mode t1 t0 t2 t3 t4 t5 t6 nop nop nop nop nop nop nop ck# ck command cke odt r tt t aof (min) t aof (max) t aofd odt r tt t aofpd (min) dont care t ransitioning r tt r tt unknown r tt on t anpd (min) t aofpd (max) 512mb: x4, x8, x16 ddr2 sdram odt timing pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 129 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 84: odt turn-on timing when entering power-down mode t1 t0 t2 t3 t4 t5 t6 nop nop nop nop nop nop nop ck# ck r tt t aon (min) t aon (max) odt r tt t aonpd (min) t aonpd (max) dont care t ransitioning r tt r tt unknown r tt on odt command t aond cke t anpd (min) 512mb: x4, x8, x16 ddr2 sdram odt timing pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 130 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 85: odt turn-off timing when exiting power-down mode t ransitioning r tt t1 t0 t2 t3 t4 ta0 ta1 nop nop nop nop nop nop nop ck# ck cke t axpd (min) odt r tt t aof (max) odt r tt t aofpd (min) t aofpd (max) command ta2 ta3 ta4 ta5 nop nop nop nop dont care r tt unknown t aof (min) indicates a break in time scale r tt on t cke (min) t aofd 512mb: x4, x8, x16 ddr2 sdram odt timing pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 131 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. figure 86: odt turn-on timing when exiting power-down mode t1 t0 t2 t3 t4 t a 0 t a 1 nop nop nop nop nop nop nop ck# ck cke t axpd (min) command t a 2 t a 3 t a 4 t a 5 nop nop nop nop t aon (min) t aon (max) r tt t aonpd (min) t aonpd (max) dont care r tt unknown r tt on indicates a break in time scale t ransitioning r tt t aond t cke (min) r tt odt odt 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 512mb: x4, x8, x16 ddr2 sdram odt timing pdf: 09005aef82f1e6e2 512mbddr2.pdf - rev. r 12/10 en 132 micron technology, inc. reserves the right to change products or specifications without notice. ? 2004 micron technology, inc. all rights reserved. |
Price & Availability of MT47H32M16HR-25E
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |